Abstract: A process for fabricating a semiconductor device is enhanced by providing a plasma etching process in which exposed metal surfaces within a plasma etching chamber (24) are protected by a ceramic layer (46). In the plasma etching process, a substrate (10) is placed on a platen (26) located within a plasma etching apparatus (22). A clamping device (40) secures the perimeter of the substrate (10) to the platen (26). The clamping device (40) includes a ceramic layer (46) overlying a metal base (44). When a plasma is ignited within the etching chamber (24), the ceramic layer (46) prevents physical contact of the plasma and the metal base (44) of the clamping device (40).

Abstract: A chemical-mechanical-polishing process in which acoustic waves are generated in the polishing slurry (18) to enable detection of an end-point in the polishing process, and to continuously clean the surface of a polishing pad (14) in a polishing apparatus (10). Acoustic waves are generated in the polishing slurry (18) by submerging a transducer (28) in the polishing slurry (18). The transducer (28) is powered by a voltage amplifier (30) coupled to a frequency generator (32). The frequency of the acoustic waves is adjusted by the frequency generator (32) to obtain optimum wave generation in the polishing slurry (18). The end-point of the polishing process is detected by a change in the acoustic wave velocity in the polishing slurry (18), which occurs when the slurry composition changes at end-point. The wave velocity is monitored by a receiver (34) submerged in the polishing slurry (18) at a predetermined distance from the transducer (28).

Abstract: A distillable, non-azeotropic solvent mixture for electronic assembly cleaning in order to adequately remove solder flux and other residues traditionally removed using CFC-based azeotropes. The mixture is heated to at least the boiling point of component A but less than the boiling point of component B. Component A vaporizes (102), forming a vapor layer above the mixture (103). Condensing elements (101) near the top of the cleaning apparatus condense the vapor (102), returning it to the heated mixture (103) to be vaporized again. The assembly (104) to be cleaned is lowered through the vapor and then immersed in the mixture (103) before being positioned in the vapor (102).

Abstract: A method for making a semiconductor device having an anhydrous ferroelectric thin-film obtained from an anhydrous sol-gel solution. An anhydrous PZT sol-gel solution is provided, wherein the sol-gel solution is prepared from lead (II) acetate anhydrous, which is heated with zirconium and titanium precursors to form a gel. The sol-gel solution is prepared without hydrolyzing the solution to obtain precursor complexes which do not contain water. The sol-gel is then applied to a semiconductor substrate and crystallized to form a ferroelectric thin-film. In a preferred embodiment, one or more steps of preparing the sol-gel solution, applying the sol-gel solution, and crystallizing the sol-gel solution are carried out in the presence of an oxygen-containing ambient.

Abstract: A copper metallization structure and process for the formation of electrical interconnections fabricated with pure copper metal is provided. The metallization structure includes an interface layer (22) intermediate to a dielectric layer (12), and a copper interconnect (30). The interface layer (22) functions to adhere the copper interconnect (30) to a device substrate (10) and to prevent the diffusion of copper into underlying dielectric layers. The interconnect layer (22) is fabricated by depositing a first titanium layer (16) followed by the sequential deposition of a titanium nitride layer (18), and a second titanium layer (20). A copper layer (24) is deposited to overlie the second titanium layer (20) and an annealing step is carried out to form a copper-titanium intermetallic layer (26).

Abstract: A transition-metal silicide process includes the formation of a boron nitride capping layer overlying a transition-metal layer. In one embodiment, a transition-metal layer (30) is deposited onto a silicon surface (22), and onto a polysilicon gate electrode (12). A capping layer (32), which can be either boron nitride or boron oxynitride is deposited onto the transition-metal layer (30), and an annealing process is carried out to form a transition-metal/silicon alloy layer (34, 36, 38) at the silicon surface (22), and on the gate electrode (12). The capping layer (32) overlies the transition-metal layer (30) during the annealing process and prevents the formation of an oxide layer at the silicon surfaces (22, 12). After the annealing process is complete, the capping layer (13) is removed by a selective wet etch process, and a second annealing step is carried out to form a transition-metal silicide layer (40, 42, 44).

Abstract: A single metal-plate bypass capacitor (10) includes a metal top plate (26) separated from a silicon substrate (12) by a thermally-grown, silicon dioxide dielectric (16) layer. An additional silicon plate (36) can be included intermediate to the metal top plate (26) and the silicon substrate (12) for multiple power supply devices. The silicon substrate (12) is electrically accessed through a metal contact pad (28) overlying a doped region (34) of the silicon substrate (12). The metal contact pad (28) is electrically isolated from the top plate (26) by an isolation structure (30). The bypass capacitor (10) is designed to be attached directly to the top surface of a semiconductor device (18), which enables the bypass capacitor (10) to be interconnected to the semiconductor device (18) by a plurality of bonding wires (25) having a minimal length. Because the capacitor dielectric (16) is formed as a very thin layer by the thermal oxidation of silicon, the self-inductance of bypass capacitor (10) is minimized.

Abstract: A semiconductor memory cell (10) having a symmetrical layout is fabricated in first and second active regions (44, 46) of a semiconductor substrate (11). A first driver transistor (16) resides in the second active region (46), and a second driver transistor (20) resides in the first active region (44). The second driver transistor (20) has a gate electrode (55) overlying a portion of the first active region (44) and is electrically coupled to the second active region (46). A thin-film load transistor (18) resides over the first active region (44), the thin-film load transistor (18) has a thin-film channel layer (23) that overlies, and is aligned with, the gate electrode (55) of the second driver transistor (20). A second portion of the thin-film channel layer (23) extends away from the first active region (44) to form a Vcc node (36). A Vcc interconnect layer (82) overlies the thin-film load transistors and the driver transistors.

Abstract: A semiconductor device (10) and process provides first and second, electrically coupled MOS transistors (14, 16) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (14). First and second gate structures (23, 25) are formed on a gate dielectric layer (26) overlying a semiconductor substrate (12). The gate dielectric layer (26) has a uniform thickness in all regions. The current gain differential between the first and second MOS transistors (14, 16) is obtained by selectively forming a dielectric intrusion layer (42) under the gate structure (23) of the first MOS transistor (14), whereas the dielectric layer (26) underlying the gate structure (25) of the second MOS transistor (16) retains the uniform thickness. The dielectric intrusion layer (42) causes a higher channel resistance in the first MOS transistor (14) which retards the current gain in the first MOS transistor (14) relative to the current gain of the second MOS transistor ( 16).

Abstract: A process for fabricating stacked gate structures (10, 11) and local interconnects (50, 52), in which portions (32, 34) of the thin-film channel layers (20, 22) are exposed by etching away portions of overlying insulating layers (28, 30). A masking layer (40) is formed to overlie the thin-film channel layers (20, 22) and the insulation layers (28, 30), and openings (42, 44) are formed in the insulation layer (40). The openings (42, 44) expose the exposed portions (32, 34) of the thin-film layers (20, 22) and portions (46, 48) of the substrate (12). Interconnects pads (50, 52) are formed to overlie the masking layer (40) and electrically contact the exposed portions of the thinfilm layers (20, 22) and the exposed portions (46,48) of the substrate (12). In regions where the insulation layers (28, 30) have not been removed, an interconnect pad (52) electrically contacts only a portion (48) of the substrate (12 ).

Abstract: A metal deposition process in which a high-purity metal film (46) is sputter deposited within a sputtering system (10) having insitu passivated metal components. A sputtering target (14) is provided having a thin aluminum coating (44) overlying a refractory metal layer (42). During operation, the aluminum coating (44) is sputtered away from the target (14) and onto exposed metal surfaces within the vacuum chamber (20) of the sputter deposition system (10). Subsequently, a semiconductor substrate (38) is placed in the sputter deposition system (10) and a high-purity metal film (46) is deposited onto the semiconductor substrate (38). Because the insitu passivation process avoid the oxidation of the passivating aluminum, refractory metal sputtered away from the target (14) adheres to the passivating aluminum layer, and does not re-deposit onto the surface of the semiconductor substrate (38) during the sputter deposition process.

Abstract: A process for forming isolation regions (20) having a self-aligned channel-stop (22) formed by implanting dopant atoms (24) through the isolation regions (22). An isolation mask (15) is formed over an active region (16) in a semiconductor substrate (10). The isolation mask can be constructed from a variety of materials including silicon nitride, silicon oxynitride, boron nitride, polysilicon, and germanium oxide. Thick isolation regions (20) are formed on either side of the isolation mask (15) and an ion implant process is carried out to form doped regions (22) in the substrate (10) immediately below the isolation regions (20). The isolation mask (15) prevents dopant atoms (24) from entering the active region (16) of the substrate (10).

Abstract: A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).

Abstract: A high-permittivity dielectric capacitor (28) having a refractory-metal oxide layer (16) framing the first electrode (14) of the capacitor (28) and separating a high-permittivity dielectric layer (24) from an insulating layer (12) underlying the capacitor (28). The high-permittivity dielectric layer (16) makes contact with the first electrode (14) through an opening (18) in the refractory-metal oxide layer (16). The refractory-metal oxide layer (16) separates the high-permittivity dielectric layer (24) from the insulating layer (12) in all regions away from the opening (18) in the refractory-metal oxide layer (16). During fabrication of the capacitor (28), when the high-permittivity dielectric layer (24) is patterned, the refractory-metal oxide layer (16) provides an etch-stop.

Abstract: A semiconductor memory cell (10) including cross coupled CMOS transistors (12, 14) wherein an N-channel transistor (20) overlies a central portion of each of a first and second active regions (13, 13') at a position intermediate to two word lines (40, 42) which overlie end portions of the active regions (13, 13'). P-channel pull-up transistors (18, 22) overlie the N-channel transistors (16, 20) and share common intermediate gate electrodes (27, 29). Staggered bit line contacts (48, 50) are formed to each active region (13, 13') adjacent to each word line (40, 42) and opposite to the N-type transistors (16, 20). Staggered Vss contacts (52, 54) are provided to each active region (13, 13') adjacent to the word lines (40, 42) and opposite to the bit line contacts (48, 50). A Vss signal is electrically coupled to the N-channel transistors (16, 20) by a doped region (21) formed in the first and second active regions (13, 13' ) which cross under the word lines (40, 42).

Abstract: A planar surface (24) is obtained in a semiconductor device (10) having regions of differing material composition by means of a non-selective planarization process. The non-selective planarization process removes insulating material and conductive material at substantially the same rate. In one embodiment of the invention, stud vias (22) are formed by the removal of portions of a conductive layer (20) overlying the surface of an interlevel dielectric layer (16). Once the conductive layer (20) has been removed, the planarization process is continued and surface portions of the interlevel dielectric layer (16) are also removed. Upon completion of the process a planar surface (24) is formed having regions of conductive material and insulating material.

Abstract: An improved semiconductor device is disclosed having a predetermined amount of solder, or other electrically conductive binder adsorbed onto the exterior package leads of the semiconductor device. A de-wettable coating comprising preferably nickel, or alternatively chromium, is plated to a superior portion of the package leads, such that, when the heat is applied to the substrate mounting end of the leads, solder desorbes from the de-wettable layer and flows down the lead to the contact pads on the mounting substrate and forms a solder joint. The amount of solder delivered to the contact pad for joint formation is determined by the thickness of the adsorbed solder layer overlying each package lead. Only enough solder is provided on each lead sufficient to form the joint thus avoiding solder bridging between adjacent contact pads.

Abstract: A non-silyated, ternary boron nitride film (18, 38) is provided for semiconductor device applications. The non-silyated, ternary boron nitride film is preferably formed by plasma-enhanced chemical vapor deposition using non-silyated compounds of boron, nitrogen, and either oxygen, germanium, germanium oxide, fluorine, or carbon. In one embodiment, boron oxynitride (BNO) is deposited in a plasma-enhanced chemical vapor deposition reactor using ammonia (NH.sub.3), diborane (B.sub.2 H.sub.6), and nitrous oxide (N.sub.2 O). The BNO film has a dielectric constant of about 3.3 and exhibits a negligible removal rate in a commercial polishing apparatus. Because of its low dielectric constant and high hardness, the ternary boron nitride film formed in accordance with the invention can be advantageously used as a polish-stop layer and as a interlevel dielectric layer in a semiconductor device.

Abstract: A semiconductor memory cell (10) includes vertically disposed MOS pass transistors (32, 34) and MOS inverters (12, 14) contained in trench structures in a semiconductor substrate (11). An MOS inverter (12) has a toroidal shared-gate electrode (48) overlying the wall surface of a first trench (36). A pass transistor (32) has a gate electrode (84) in a third trench (40). A first buried drain region (62) resides in the substrate (11) adjacent to the first trench (36), and is located a first distance from the substrate surface. A second buried drain region (64) resides in the substrate (11) adjacent to the second trench (32), and is located a second distance from the substrate surface. The inverter (12) and the pass transistor (32) are electrically coupled by the first and second buried layers (62, 64). The channel length (90) of the driver transistor (16) in the inverter (12) and the pass transistor (32) is determined by the first and second distances, respectively.

Abstract: An alignment key (10) in a semiconductor substrate (40) is fabricated to display high optical contrast, and to prevent the diffusion of ionic contaminants through the alignment key (10) and into underlying portions of the semiconductor substrate (40). The alignment key (10) defines an enclosed structure formed by first and second metal layers (14, 20) which are electrically coupled by a filled via (22). A dielectric layer (42) is disposed between the metal layers (14, 20). A passivation layer (16) overlies an edge portion of the upper metal layer (14), however, the central portion of the upper metal layer (14) is bare. Slots (11, 12) in the upper metal layer (14) expose a portion of the lower layer (20) through the dielectric material (42). A high contrast scan signal (24) is generated as a continuous-wave laser beam traverses across the upper metal layer (14) and the slots (11,12).