Patents Represented by Attorney, Agent or Law Firm Jeffrey S. Draeger
  • Patent number: 6976131
    Abstract: A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having a private cache, and a shared cache. An internal snoop bus is coupled to each private cache and the shared cache to communicate data from each private cache to other private caches and the shared cache. In another embodiment, an apparatus includes a plurality of processor cores and a plurality of caches. One of the plurality of caches maintains cache lines in two different modified states. The first modified state indicates a most recent copy of a modified cache line, and the second modified state indicates a stale copy of the modified cache line.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Vladimir Pentkovski, Vivek Garg, Narayanan S. Iyer, Jagannath Keshava
  • Patent number: 6804632
    Abstract: Distribution of processing activity across processing hardware based on power consumption and/or thermal considerations. One embodiment includes a plurality of processing units and a monitor to obtain monitor (e.g., power consumption, or temperature or some combination thereof) values from the processing units. The monitor transfers a process from one processing unit to another in response to the monitor values from the processing units.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: October 12, 2004
    Assignee: Intel Corporation
    Inventors: Doron Orenstien, Ronny Ronen
  • Patent number: 6804735
    Abstract: A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: October 12, 2004
    Assignee: Intel Corporation
    Inventors: Gurbir Singh, Robert J. Greiner, Stephen S. Pawlowski, David L. Hill, Donald D. Parker
  • Patent number: 6804800
    Abstract: A method and apparatus for detecting and in some cases recovering from errors in a source synchronous bus. One embodiment of a disclosed apparatus includes a plurality of strobe inputs to receive a plurality of strobe signals. A plurality of data inputs receive a plurality of data signals transmitted in a source synchronous manner in conjunction with the strobe signals. Bus control logic produces an externally visible indication that an error has occurred if a glitch on one or more of the plurality of strobe signals is detected.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: October 12, 2004
    Assignee: Intel Corporation
    Inventor: Pablo M. Rodriguez
  • Patent number: 6799268
    Abstract: A branch ordering buffer. One disclosed apparatus includes a processor state management circuit to maintain a primary state and a shadow state, each of the primary state and the shadow state including mappings from logical registers to physical registers. The primary state is a speculative state. This disclosed apparatus also includes a branch ordering circuit to prevent the shadow state from advancing beyond a branch instruction until commitment of the branch instruction.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 28, 2004
    Assignee: Intel Corporation
    Inventors: Darrell D. Boggs, Shlomit Weiss, Alan Kyker
  • Patent number: 6742160
    Abstract: Checkerboard parity techniques are disclosed. In one embodiment, a bus agent has a multi-pumped interface to generate in N elements in N phases. Each element includes N sub-elements, each sub-element being a fixed portion of an element. A parity generation circuit generates parity signals that are each a function of N sub-elements, a different sub-element from each phase.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: May 25, 2004
    Assignee: Intel Corporation
    Inventor: Robert J. Greiner
  • Patent number: 6681320
    Abstract: Causality-based memory ordering in a multiprocessing environment. A disclosed embodiment includes a plurality of processors and arbitration logic coupled to the plurality of processors. The processors and arbitration logic maintain processor consistency yet allow stores generated in a first order by any two or more of the processors to be observed consistent with a different order of stores by at least one of the other processors. Causality monitoring logic coupled to the arbitration logic monitors any causal relationships with respect to observed stores.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: January 20, 2004
    Assignee: Intel Corporation
    Inventor: Deborah T. Marr
  • Patent number: 6664792
    Abstract: A system including at least one electronic component and a battery check circuit. When a power consumption level of the at least one electronic component is increased, the battery check circuit determines whether to provide power from a battery to the at least one electronic component by comparing a power level of the battery to a first power level.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: December 16, 2003
    Assignee: Intel Corporation
    Inventor: Don J. Nguyen
  • Patent number: 6636957
    Abstract: A method and apparatus for configuring and/or initializing memory devices. A disclosed method initializes a memory controller and a plurality of memory controller configuration registers. Serial identification numbers are assigned to memory devices coupled to the memory controller. Additionally, groups of device identification numbers, which are based at least in part on the memory device sizes, are assigned to the memory devices, and the memory devices are enabled.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: October 21, 2003
    Assignee: Intel Corporation
    Inventors: William A. Stevens, Puthiya K. Nizar
  • Patent number: 6608515
    Abstract: A dynamic feedback bias circuit. A system utilizing the dynamic bias circuit includes a first bus agent and a second bus agent. The first bus agent generates a first signal having a first voltage swing. The second bus agent has a core which operates at a core operating voltage, the core operating voltage having an amplitude less than the first voltage swing. The second bus agent has an input device which receives the first signal from the first bus agent. The input device of the second bus agent is biased by the dynamic feedback bias circuit to provide a core signal with a voltage swing approximately equal to or less than the core operating voltage.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: August 19, 2003
    Assignee: Intel Corporation
    Inventor: Babak A. Taheri
  • Patent number: 6565369
    Abstract: An improved stacking connector. The connector includes a plug portion and a receptacle portion. The plug portion includes a plug signal pin and a plug impedance control pin located adjacent to the plug signal pin. The receptacle portion includes a receptacle signal pin for engaging the plug signal pin when the plug portion and the receptacle portion are in a mated position. The connector also includes an impedance control shield which is located adjacent to the plug signal pin or receptacle signal pin.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: May 20, 2003
    Assignee: Intel Corporation
    Inventors: Hugo K. Schulz, Leonard O. Turner
  • Patent number: 6549867
    Abstract: A power supply feed-forward compensation technique using power consumption hints. One embodiment includes a power estimator to generate a power consumption hint that indicates a power consumption level of a component. A transfer function compensation circuit generates a power supply adjustment signal as a function of the power consumption hint and a power transfer function to the component.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: April 15, 2003
    Assignee: Intel Corporation
    Inventor: Ronald D. Smith
  • Patent number: 6453375
    Abstract: A method and apparatus that may be used to obtain coherent accesses with posted writes. One method disclosed involves returning a semaphore indicator in an unlocked state and setting the semaphore indicator to a locked state in response to a semaphore indicator read when the semaphore indicator is in an unlocked state. A cycle for a target from a source is stored in an interface circuit, and the semaphore indicator is cleared to the unlocked state after the cycle completes to the target.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: September 17, 2002
    Assignee: Intel Corporation
    Inventors: Michael N. Derr, Karthi R. Vadivelu
  • Patent number: 6445240
    Abstract: A dynamic feedback bias circuit. A system utilizing the dynamic bias circuit includes a first bus agent and a second bus agent. The first bus agent generates a first signal having a first voltage swing. The second bus agent has a core which operates at a core operating voltage, the core operating voltage having an amplitude less than the first voltage swing. The second bus agent has an input device which receives the first signal from the first bus agent. The input device of the second bus agent is biased by the dynamic feedback bias circuit to provide a core signal with a voltage swing approximately equal to or less than the core operating voltage.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: September 3, 2002
    Assignee: Intel Corporation
    Inventor: Babak A. Taheri
  • Patent number: 6438686
    Abstract: A method and apparatus for eliminating contention with dual masters. One method disclosed disables a default bus master, and tests for a second bus master. If the second bus master fails to respond, the default bus master is enabled.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: August 20, 2002
    Assignee: Intel Corporation
    Inventors: Gregory M. Daughtry, Hieu T. Tran, Srithar Ramesh, Andrew J. McRonald
  • Patent number: 6434001
    Abstract: A heat exchanger for a computing device and a docking station. The heat exchanger includes a first heat transfer element and a second heat transfer element. The first heat transfer element has a portion thermally coupled to an electronic component. The first and the second heat transfer element conformally engage each other yet are removable from each other.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: August 13, 2002
    Assignee: Intel Corporation
    Inventor: Rakesh Bhatia
  • Patent number: 6434016
    Abstract: A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: August 13, 2002
    Assignee: Intel Corporation
    Inventors: Ming Zeng, Sanjay Dabral
  • Patent number: 6430697
    Abstract: A method and apparatus for reducing data return latency of a source synchronous data bus by detecting a late strobe and enabling a bypass path. A disclosed apparatus includes a core portion clocked by a core clock and an interface circuit. The interface circuit is coupled to deliver a burst cycle to said core portion. The burst cycle includes a set of sequentially delivered bits that are transmitted with corresponding sequential edges of a transfer clock. Each bit of the burst cycle is delivered either via one of a set of receiving latches coupled in parallel to a data input or via a bypass path that bypasses the set of receiving latches.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: August 6, 2002
    Assignee: Intel Corporation
    Inventor: Harry Muljono
  • Patent number: RE39284
    Abstract: A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU runs an operating system having a power management virtual device driver (PMV×D) responsible for performing idle detection for devices. The PMV×D performs idle detection using event timers that provide an indicator as to the activity level. The PMV×D places idle local devices in a reduced power consumption state when no activity has occurred for a predetermined period of time.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventor: Suresh K. Marisetty
  • Patent number: RE38388
    Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: January 13, 2004
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Peter D. MacWilliams, Stephen S. Pawlowski, Michael W. Rhodehamel