Abstract: The invention is directed to a method for manufacturing semiconductor device. The method comprises steps of providing a substrate and then forming a dielectric material-containing device over the substrate. A plasma vapor deposition process is performed to form a dielectric layer over the substrate. A first baking process is performed.

Abstract: A thin film transistor array substrate applied to a liquid crystal display device is provided with at least two storage capacitance lines electrically connected with each other. These electrically connected storage capacitance lines, which belong to two adjacent pixels at two sides of a scanning line, are connected with contact holes and conductive layer, and may eliminate the lateral crosstalk of the liquid crystal display device.

Abstract: A rational number frequency multiplier circuit and a method for generating rational number multiple frequency are disclosed. The circuit receives a plurality of input signals having the same frequency and different phase, and outputs at least one multiple frequency signal. The rational number frequency multiplier circuit includes a frequency divider module, for receiving and dividing the input signals to output frequency-divided signals having the same frequency and different phase; a first phase synthesis module and a second phase synthesis module for receiving and synthesizing the frequency-divided and input signals respectively into a plurality of first pulse period signals and second pulse period signals; and an adder for receiving and combining the first pulse period signals and the second pulse period signals into the multiple frequency signal according to the desired multiplication of the frequency.

Abstract: A programmable detection adjuster is disclosed. The programmable detection adjuster comprises a bandgap and an adjusting circuit. The bandgap comprises a power input terminal, a voltage output terminal, a main resistance and a plurality of resistors. The adjusting circuit comprises a plurality of adjusting resistors, a plurality of transistor switches, a logic controller and detection circuits; said adjusting resistors connected to the main resistance of the bandgap in series. The adjusting resistors are respectively connected to the transistor switch in parallel. The transistor switches are connected to the logic controller. The logic controller is respectively connected to the detection circuits. The detection circuit detects the corresponding resistances in the detection circuit and outputs a voltage level to the logic controller to enable the logic controller to control a conduction of the transistor switches according to a logic conversion table.

Abstract: A backlight module comprising a light guild plate, at least one lamp, a lower frame, at least one turning holder, a locating block and an upper frame is provided. The lower frame is used for carrying the light guild plate and the lamp. The light guide plate has light incidence planes and light emergence planes, and the lamp is disposed beside at least a part of the light incidence planes. The lamp has at least one turning angle, and the turning holder covers the turning angle of the lamp. The locating block is disposed on the turning holder, and the upper frame is disposed on the lower frame and exposes the light emergence plane. The upper frame has a locating opening, and the locating block is embedded in the locating opening. The backlight module provides three-dimensional preservation to preserve the lamp from the damage caused by external impact.

Abstract: A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed thereon. The second circuit layer comprises a plurality of bonding pads and traces. The traces are electrically connected to the corresponding bonding pads. Furthermore, the bonding pads are used for being connected to the bumps. The second circuit layer of the interposer is physically and electrically connected to the first circuit layer of the first substrate, and the second substrate and the first substrate are made of different materials.

Abstract: A display driving circuit having a plurality of driving stages and driving lines is provided. The driving stages are electrically coupled in serial, and each of the driving stages comprises a conducting path for transmitting an electric signal from the previous driving stage to the next driving stage via the current driving stage. Each of the driving lines respectively corresponds to a driving stage and electrically connects to an output terminal of the corresponding driving stage. The display driving circuit is characterized in that a redundant device is only installed in one part of the driving stages. The redundant device is capable of supplying an extra conducting path to transmit an electric signal from the previous driving stage to the next driving stage via the current driving stage while the original conducting path in the corresponding driving stage is broken.

Abstract: A thin film transistor array substrate and repairing methods thereof are disclosed. The thin film transistor array substrate comprises openings in each pixel electrode, each capacitor electrode and each common line. The openings of the capacitor electrode and the common line are located in the opening of the pixel electrode. The opening of the capacitor electrode exposes a portion area of the capacitor electrode and the common line. The pixel electrode is coupled to the common line through a connecting conductive layer. The MII storage capacitor Cst is formed by the pixel electrode and the capacitor electrode. When the MII storage capacitor Cst fails, the MII storage capacitor Cst can be switched to the MIM storage capacitor Cst by laser repairing.

Abstract: A dynamic mask module is disclosed, which comprises a microcomputer system, a mask pattern generator and a light source. The mask pattern generator is disposed over a substrate and electrically connected to the microcomputer system. The microcomputer system transmits an image signal to the mask pattern generator. The light source is disposed over the mask pattern generator to a photo-resist layer on the substrate. The mask pattern generated by the dynamic mask module is a dynamic image and the mask pattern can be changed on anytime. In addition, the manufacturing cost can be and the manufacturing time can be reduced.

Abstract: An active matrix organic electro-luminescent display (AMOELD) panel comprising a substrate, a pixel structure, an organic light-emitting layer and a cathode pattern layer is provided. The pixel structure layer is disposed over the substrate. The pixel structure layer further comprises an active device matrix and an anode pattern layer. The organic light-emitting layer covers at least the anode pattern layer and comprises at least a first organic light-emitting pattern, at least a second organic light-emitting pattern and at least a third organic light-emitting pattern. The cathode pattern layer is disposed on the organic light-emitting layer. The cathode pattern layer comprises a first cathode pattern disposed on the first organic light-emitting pattern, a second cathode pattern disposed on the second organic light-emitting pattern and a third cathode pattern on the third organic light-emitting pattern. Furthermore, the first, the second and the third cathode pattern are not connected to each other.

Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are formed using the same conductive layers.

Abstract: A light source device and projector using the same is provided. The light source device includes multiple light source modules and a multi-channel optical light tube. The multi-channel optical light tube includes multiple channels, each of which has a light guiding portion and corresponds to one or more of the light source modules. The light source module transmits the output light to the corresponding light channel, and the light guiding portion of each light channel is provided with a reflective surface for combining the light input through the light channels to the multi-channel optical light tube, thus providing the output of the light source device.

Abstract: A method of fabricating a semiconductor device is provided. Before covering the isolation structures with a conductive layer, a material layer is formed on the isolation structures. The fluid-like material layer allows the material layer formed between the isolation structures to be thicker than that formed on the top of the isolation structures. The isolation structures are then effectively etched back. The material layer at the top of the isolation structures is removed and a portion of isolation structures is also removed to lower the height of the isolation structures.

Abstract: A chip package including a heat spreader, a circuit substrate, locating structures, a chip, wires, and an encapsulating compound is provided. The heat spreader has a bonding surface, and the circuit substrate is disposed on the bonding surface of the heat spreader. The circuit substrate has an opening, which exposes a portion of the bonding surface. The locating structures are disposed on the heat spreader for fixing the circuit substrate and attaching the circuit substrate to the bonding surface closely. The chip is disposed on the bonding surface exposed by the opening, and the wires are coupled between the chip and the circuit substrate. The encapsulating compound is disposed on the bonding surface exposed by the opening for covering the chip, the wires, and a portion of the circuit substrate. The chip package has high reliability and high yield of processing.

Abstract: A method for fabricating an interconnection in an insulating layer on a wafer is described. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.

Abstract: A method for adjusting a clock and an electronic device with clock adjusting function are provided. In the method of adjusting the clock, the electronics device is driven with a first clock when the electronic device is during the reset-inactive state. Then, the electronic device is driven with a second clock when the electronic device receives a reset signal. Wherein, the cycle of the second clock is larger than that of the first clock.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: A fluid ejection device, a method and an operation method thereof are disclosed. The fluid ejection device includes a substrate, a beam and an activation pad. The substrate has an orifice, and the beam includes a fixed portion and a cantilever portion and is disposed over the substrate, wherein the cantilever portion is disposed over the orifice. Furthermore, the activation pad is disposed between the cantilever portion of the beam and the substrate. Because the fluid ejection device of the present invention is fabricated by using micro-electromechanical technology, and therefore it possible to obtain a fluid ejection device capable of ejecting the fluid from the orifice at a high-speed and also the quantity fluid ejected can be very small.

Abstract: A circuit layout structure for a chip is provided. The chip has a bonding pad area, a nearby device area, and a substrate. The circuit layout structure essentially comprises a plurality of circuit layers, a plurality of dielectric layers and a plurality of vias. The circuit layers are sequentially stacked over the substrate. Each dielectric layer is sandwiched between a pair of adjacent circuit layers. The vias pass through the dielectric layers and electrically connect various circuit layers. The farthest circuit layer away from the substrate has pluralities of bonding pads within the bonding pad area. The bonding pads near the device area overstrides at least one non-signed circuit layer through the furthest circuit layer away from the substrate and electrically connects to a circuit layer nearer the substrate with vias. The circuit layout structure can avoid a direct conflict of signals between the power/ground circuits and the signal circuits.

Abstract: An erasing method for a non-volatile memory is provided. The method includes the following two major steps. (a) A first voltage is applied to the odd-numbered select gates of each memory row and a second voltage is applied to the even-numbered select gates of each memory row such that the voltage difference between the first voltage and the second voltage is large enough for the electrons injected into the floating gate of the memory cells to be removed via the select gate. (b) A switchover operation is performed so that the first voltage is applied to the even-numbered select gates of each memory row and the second voltage is applied to the odd-numbered select gates of each memory row such that the electrons injected into the floating gates of the memory cells are pulled away via the select gates to turn the memory cells into an erased state.