Abstract: An apparatus for monitoring fiber-fault in an optical networks, such as a passive optical networks, suitable for monitoring at least one fiber path in connection. The apparatus includes at least one fiber grating, having an individual central wavelength and coupling with the fiber networks; at least one reflection unit; and at least one optical gain medium unit, which is coupled between the fiber grating and the reflection unit, so as to produce at least one optical signal. The optical signal is amplified by allowing the optical signal to transmit to-and-fro between the fiber grating and the reflection unit, and then inducing excitation. The optical signal corresponding to the reflection unit has a corresponding spectrum for use in monitoring the optical network.

Abstract: A method of operating a P-channel memory is described. The P-channel memory includes a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and the gate, and the first and second sources/drains formed in the substrate adjacent to two sides of the charge trapping structure. An erasing operation is performed by applying a first voltage to the second source/drain, applying a second voltage to the first source/drain, applying a third voltage to the gate, and applying a forth voltage to the substrate. Hot holes are injected in the charge trapping structure to erase the P-channel memory by the tertiary hot hole mechanism. The absolute value of the voltage differential between the third and the forth voltages is equal to, or less than 6V, and the second voltage is smaller than the third voltage.

Abstract: An inkjet printer identification circuit is provided. It includes a plurality of control lines, a control circuit providing a control signal to the plurality of control lines, and an identification module including an identification unit. The identification unit includes at least a control input terminal, an output terminal and at least a data input terminal. The data input terminal is coupled to a memory unit. The control input terminal is coupled to one of the plurality of control lines. The identification unit is responsive to the control signal for determining and outputting a content stored in the memory unit via the output terminal. The control circuit identifies the status of the identification unit based on the received content stored in the memory unit.

Abstract: A DC level wandering cancellation circuit is provided. The DC level wandering cancellation circuit comprises a low pass filter, for receiving an input voltage; a high pass filter coupled to the low pass filter; an amplifier coupled to the high pass filter for receiving a reference voltage and an output signal of the high pass filter; a comparator coupled to the amplifier for receiving an output signal of the amplifier to compare the reference voltage with the output signal of the amplifier; a resistor coupled between outputs of the high pass filter and the amplifier; a control logic coupled to the comparator for receiving a compared result from the comparator; and a switching means coupled between the high pass filter and the output of the amplifier. The switching means is turned on for a predetermined interval by the control logic according to the compared result.

Abstract: A pixel structure and fabricating method thereof is provided. The pixel structure includes a scan line, a data line, an active component, a plurality of transparent capacitance electrodes and a pixel electrode. First, an active component, a scan line and a data line are formed over a substrate, wherein the active component is electrically connected to the scan line and the data line. In addition, a plurality of transparent capacitance electrodes are formed over the substrate. Next, a pixel electrode is formed over the transparent capacitance electrode and electrically connected to the active component. Thus, the pixel electrode and the transparent capacitance electrodes constitute a multilayer pixel storage capacitor. Since the pixel storage capacitor is comprised of transparent material, and being a multilayer structure, the capacitance of the pixel storage capacitor and the aperture ratio of the pixel structure respectively are increased.

Abstract: A flash memory cell and a method for fabricating the same are described. The flash memory cell comprises a substrate, a select gate, a floating gate, a gate dielectric layer, a high-voltage doped region and a source region. The substrate has a first opening thereon and a second opening in the first opening. The select gate is on the sidewall of the first opening, and the floating gate is on the sidewall of the second opening. The gate dielectric layer is between the select/floating gate and the substrate. The high-voltage doped region is in the substrate under the second opening, and the source region is in the substrate beside the first opening. In the method of fabricating the flash memory cell, the select gate and the floating gate are simultaneously formed on the side walls of the first opening and the second opening, respectively.

Abstract: A circuit structure for a package substrate or a circuit board is provided. The circuit structure has a dielectric layer with an upper surface and a lower surface, at least a first line and at least a second line. The first line is disposed on the dielectric layer on which a base of the first line is aligned with the upper surface. In addition, the second line is disposed on the dielectric layer on which a base of the second line is embedded below the upper surface. Since the second line is embedded into the dielectric layer, the distance with a reference plane is reduced and the crosstalk between the signals is further effectively reduced.

Abstract: A method of manufacturing a thin film transistor is described. A polysilicon island is formed over a substrate. A gate insulating layer is formed over the substrate to cover the polysilicin island. A gate is formed on the gate insulating layer above the polysilicon island. A passivation layer is formed over the substrate to cover the gate and the gate insulating layer. An ion implanting process is carried out to form a source/drain in the polysilicon island beside the gate, wherein a region between the source and the drain is a channel. After the first passivation layer is removed, a patterned dielectric layer is formed over the substrate, wherein the dielectric layer exposes a portion of the source/drain. A source/drain conductive layer is formed over the dielectric layer and is electrically connected to the source/drain.

Abstract: A method of forming an ultra-thin wafer level stack package and structure thereof are provided. The method includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

Abstract: A method of enhancing the adhesion between photoresist material and a substrate that can be applied to fabricate bumps on the substrate is provided. The bump fabrication process uses at least photoresist materials each having a different viscosity. A photoresist material having a smaller viscosity, that is, a higher fluidity, is permitted to contact a passivation layer so that all the gaps on the surface of the passivation layer are completely filled and a strong bond is formed between the photoresist layer and the passivation layer. With all the gaps on the substrate completely filled, solder material is prevented from filling the gaps to form a conductive bridge between neighboring bonding pads in a subsequent bump fabrication process.

Abstract: A data communication circuit of a SDRAM for data communication comprises a plurality of data lines coupled to a plurality of data pins. The number of the data lines, according to an embodiment of the present invention, is less than the number of the data pins. When the data communication circuit receives/outputs data, one of the LDQM pin and the UDQM pin are enabled to receive/output a first part of the data. The other LDQM pin and the UDQM pin are enabled. Accordingly, the data communication circuit of the SDRAM, according to an embodiment of the present invention, is capable of transmitting more data using a bus with a narrow width.

Abstract: A security activation method for wireless identification for controlling an electronic device system boot up includes the following steps: receiving a first identification signal, designating a corresponding first identification code as a pre-established account, transmitting a confirmation signal to a wireless transmission device corresponding to the pre-established account, receiving an authorization signal from the device, receiving a second identification signal, and comparing a corresponding second identification code with the pre-established account; if the second identification signal is the same as the pre-established account, determine whether the system accesses a boot buffer inside the electronic device; and having the following corresponding implemented actions: if the system accesses the boot buffer inside the electronic device, the system boots and transitions into operational mode; and if the system doesn't access the boot buffer, the system is shut down and receives an automatic command for sy

Abstract: A pixel structure controlled by a scan line and a data line on a substrate is provided. The pixel structure comprises a thin film transistor, a resistance wire, a first pixel electrode, and a second pixel electrode, which are disposed on the substrate. Additionally, the thin film transistor is electrically connected to the scan line, the data line, and the resistance wire. Further, the first pixel electrode is electrically connected to the thin film transistor and the second pixel electrode is electrically connected to the thin film transistor by the resistance wire. Especially, a method of manufacturing a pixel structure is also provided.

Abstract: A method for accessing a single port memory is provided. A single port memory is used as a line buffer and divided into a plurality of memory blocks. The line buffer data is written into or read out from these memory blocks by turns with a special sequence corresponding to the operation mode; for example, a normal mode or a PLM mode. Therefore, the line buffer data can be written into or read out from the line buffer at the same time, and the size and cost of integrated circuit can be reduced.

Abstract: A boost DC/DC converter, including a mask circuit, a switched boost circuit, a pulse width modulation (PWM) circuit and an AND gate, is provided. The mask circuit is used to output a mask signal according to a load current. In the present invention, the system can selectively operate in the pulse width modulation mode, the pulse frequency modulation (PFM) mode or the mixed pulse mask mode according to the mask signal corresponding to the load current when the system is under light load, medium load or heavy load respectively, so as to achieve optimal system efficiency.

Abstract: A method of fabrication a non-volatile memory is provided. A stacked structure is formed on a substrate, the stacked structure including a gate dielectric layer and a control gate. Then, a first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed on the top and sidewalls of the stacked structure and the exposed substrate. Thereafter, a pair of charge storage layers are formed over the substrate to respectively cover a portion of the top and sidewalls of the stacked structure, and a gap exists between each of the charge storage layers.

Abstract: A back plate structure comprises a back plate body, at least a supporting beam and a plurality of heat dissipation members, wherein the supporting beam is fixed on a back of the back plate body and the heat dissipation members are disposed on the supporting beam. The supporting beam has a central protrusion portion and a peripheral portion. The heat dissipation members are disposed on an upper surface of the peripheral portion or on a sidewall of the central protrusion portion or into an inner portion of the central protrusion portion. Because the heat dissipation members are disposed on the supporting beam, the heat dissipation area of the present invention can be increased and therefore the heat dissipation efficiency of the plasma display apparatus can be effectively promoted. Therefore, the service life of the plasma display apparatus can be increased and also the display performance thereof can be enhanced.

Abstract: A method of fabrication deep trench capacitors includes forming a plurality of deep trenches in a substrate. A bottom electrode is formed in the substrate surrounding the bottom of each deep trench. A capacitor dielectric layer and a first conductive layer are formed at the bottom of each deep trench. A collar oxide layer is formed on the sidewall of the deep trench exposed by the first conductive layer. A second conductive layer fills each deep trench. An opening is formed in a region predetermined for an isolation structure between adjacent deep trenches, wherein the depth of the opening is greater than that of the isolation structure. An isolation layer is filled in the opening.

Abstract: Auto-recovery wafer testing apparatus and wafer testing method are provided. The wafer testing apparatus includes a main system, a tester and a real-time accessing module. The main system controls the process of the wafer testing. The tester is electrically coupled to the main system for receiving commands from the main system to perform testing on a plurality of chips sequentially and output the testing data correspondingly. The real-time accessing module is electrically coupled to the tester for simultaneously accessing the testing data. In an event when the testing is accidentally interrupted, the tester can produce auto-recovery data according to the testing data saved in the real-time accessing module, and continue testing, based on the auto-recovery data, from the chip being last but incompletely tested. The use of the wafer testing apparatus and method can save testing time and enhance the production efficiency.

Abstract: A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.