Abstract: Hardware and partition information of an existing LPAR system is collected and stored in a first system plan file. The first system plan file is applied to a partition planning tool. The partition planning tool identifies hardware to be reused in a second LPAR system and filters hardware to be excluded from the second LPAR system. The partition planning tool creates a plan for the second LPAR system using the identified hardware to be reused and the partition information. The created plan for the second LPAR system is applied to a partition deployment tool to partition the second LPAR system. The created plan for the second LPAR system is used to move and place hardware to be reused in the second LPAR system.

Abstract: Conflict resolution of web application keyboard shortcuts implementation includes a web application being loaded in a web browser and application keyboard shortcuts for the web application are registered with the web browser. The web browser identifies application keyboard shortcuts for the web application that conflict with keyboard shortcuts for the web browser. Then the web browser resolves each conflict.

Abstract: A method and apparatus are provided for implementing optimized speed sorting of microprocessors at wafer test. A combination of speed-predicting metrics are measured early in the manufacturing process and are applied to a unique algorithm to properly sort parts into appropriate speed bins. The method significantly improves the accuracy of predicting the chip speed over conventional speed-predicting methods.

Abstract: A process combines multiple grouping sets into single rollup sets with depth lists defining the levels of grouping that must be performed. Grouping sets are identified that are contained within other sets and combined into single rollups with depth lists. Cube aggregation conversion to rollup aggregation is provided for optimizing database query processing. Natural sets of rollup hierarchies within a cube are recognized and the cube is converted into those rollup hierarchies. Once converted, the rollup aggregation is performed to significantly reduce required processing.

Abstract: A method, and apparatus are provided for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. On random occasions a selection mechanism is changed for first holding up all requests and then a random selection is made. Then a round robin selection mechanism is used for further requests. A livelock-preventing selection mechanism includes a pair of linear feedback shift registers (LFSRs), each LFSR for generating pseudo random values.

Abstract: An enhanced method and apparatus are provided for tracking and managing a plurality of packagings, particularly packagings containing radioactive and fissile materials. A radio frequency identification (RFID) surveillance tag is provided with an associated packaging. The RFID surveillance tag includes a tag body and a back plate including predefined mounting features for mounting the surveillance tag to the associated packaging. The RFID surveillance tag includes a battery power supply. The RFID surveillance tag includes a plurality of sensors monitoring the associated packaging including a seal sensor. The seal sensor includes a force sensitive material providing a resistivity change responsive to change in a seal integrity change of the associated packaging. The resistivity change causes a seal integrity tag alarm. A tag memory stores data responsive to tag alarms generated by each of the plurality of sensors monitoring the associated packaging.

Abstract: Dynamic processor allocation is implemented based upon bitmap data density. A bitmap index is used to process the query. A bitmap is created for the query. The bitmap is partitioned into single I/O operations. A variable partition size is provided based upon data density. Data density for each partition is calculated. Processors are assigned based upon data density of each partition. Then the partitions are processed and query results are returned.

Abstract: A method, and structures are provided for implementing differential signal circuit board electrical contact. A removable member including a pair of independent electrical contacts is removably received within an associated contact-receiving cavity on the circuit board. The contact-receiving cavity includes a mating pair of circuit board pads. A respective dielectric is provided between each of the pair of independent electrical contacts and the mating pair of circuit board pads.

Abstract: A computer system, computer program product, and method implement dynamic physical memory reallocation. A system management interface (SMI) Handler and an Operating System (OS) are arranged for exchanging communications. Periodically the SMI Handler queries the operating system to identify a percentage of available memory currently being utilized. Responsive to the identified percentage of available memory currently being utilized, physical memory is dynamically reallocated.

Abstract: An enhanced mechanical design for laminar weak-link mechanisms with centimeter-level travel range and sub-nanometer positioning resolution is provided. A multiple parallelogram weak-link structure includes a predefined pattern of a plurality of perpendicularly arranged groups of connecting links, each link having at least one pair of weak-link connections. Each of the plurality of perpendicularly arranged groups includes a terminal for mounting to a fixed base. The multiple parallelogram weak-link structure includes a moving part for mounting on a carriage, providing precisely controlled movement with stability in one direction. A two-dimensional (2D) ultra-precision scanning stages assembly for x-ray nanoprobe applications includes multiple redundantly constrained weak-link structures, a vertical ultra-precision positioning stage, and a horizontal ultra-precision positioning stage.

Abstract: A method and circuit for implementing a coded time domain transmission distance meter, and a design structure on which the subject circuit resides are provided. A first transmitter module connected to a cable at a first point or power outlet, generates and sends a testing coded pulse onto the power cable. A second receiver module connected to the cable at a second point, receives the testing coded pulse, and returns a receiver response coded pulse to the transmitter module. The first transmitter module determines the round-trip elapsed time, subtracts a receiver latency time, and calculates a distance to the second receiver module. Encoded in the testing coded pulse are data representing the last calculated distance. Both the first transmitter module and the second receiver module include a display for displaying the calculated distance.

Abstract: A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first layer of silicon dioxide dielectric above the first metal layer. A second layer of silicon dioxide dielectric is deposited and the vertical air gap is sealed. A next trace layer is etched from the second layer of silicon dioxide dielectric and a via opening is etched from the second and first layers of silicon dioxide dielectric. Then metal is deposited into the next trace layer and metal is deposited into the via opening.

Abstract: A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including the circuitry to be protected. A change in the capacitor value results responsive to the semiconductor chip being thinned, which is detected and a tamper-detected signal is generated.

Abstract: A method and enhanced connector guide block structures implement robust connector assembly including robust Surface Mount Technology (SMT) connector assembly. A connector guide block includes a printed wiring board (PWB) mating face including at least one mounting screw hole provided within a mounting portion for receiving a mounting screw. The connector guide block is assembled with a printed wiring board (PWB) by inserting a respective non-bonding screw through an aligned opening in the PWB into guide block mounting hole and a gap is defined from an upper surface of the PWB below the guide block mounting portion. The gap is filled with an electrically nonconductive underfill material and cured. Another connector guide block structure includes an upper connector guide block portion and a lower connector guide block portion with a gap between the guide block portions filled with a selected electrically nonconductive underfill material and cured.

Abstract: A memory controller and methods implement minimized latency and maximized reliability when data traverses multiple buses. The memory controller includes a dynamic random access memory (DRAM) error correcting code (ECC) checking and correcting circuit and a high speed bus (HSB) ECC checking and correcting circuit. In a first mode for implementing minimized latency, read data is applied directly to the DRAM ECC checking and correcting circuit, bypassing the HSB ECC checking and correcting circuit. In a second mode for implementing maximized reliability, the read data is applied through the HSB ECC checking and correcting circuit to the DRAM ECC checking and correcting circuit.

Abstract: A method and apparatus are provided for implementing frame alteration commands in a communications network processor. A set of frame alteration instruction templates is defined. A frame alteration instruction template is identified based upon the packet type recognition result of a received packet. A frame alteration instruction stream is generated utilizing the frame alteration instruction template. Each of the frame alteration instruction templates includes different frame alteration commands to be performed on a packet. Pointers to indirect data bytes to be inserted in a packet are stored in the frame alteration instruction templates. The generated frame alteration instruction stream is used by hardware to provide frame alterations.

Abstract: An elutriation column is installed in a separation tank. The elutriation column includes a vertical separation column having a first side feed arm and a second side overflow arm spaced above the first side feed arm. Water is forced upwardly through the vertical separation column at a controllable velocity. A solid feed mixture is fed through the first side feed arm to the vertical separation column. Water from the tank rising in the vertical separation column at the controlled velocity causes targeted floater materials to move upwardly in the vertical separation column and heavier sinker materials to continue to sink. The floater materials flow from an outlet in the side of the separation tank into the recovery tank. At a discharge, lower end of the vertical separation column, the heavier sinker materials are removed from the separation tank. A mechanism is provided for purging undesirable materials that can cause plugging from the feed arm.

Abstract: Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.

Abstract: A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.

Abstract: A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instruction. When a trace instruction is identified by the APU, the APU signals the CPU with a pipeline stall signal for stalling the CPU and checks for an enabled trace engine as specified by the trace instruction. When the trace engine for the trace instruction is enabled, then the trace data is written into a trace buffer. The APU signals the CPU with an op done signal for allowing the CPU to continue with instruction processing.