Abstract: Apparatus and method are provided that can be advantageously included in a timing phase-locked loop for finally adjusting the period of a timing signal being controlled by that loop. The loop filter receives the timing signal and generates a loop error signal indicative of whether the period of the timing signal should be held the same, increased or decreased. A strobe signal is also generated each time that the timing signal is to be so corrected. The error signal and strobe signal are provided to a function generator such as a state machine. Each time that the function generator is strobed by the strobe signal, it produces a count signal whose value is representative of N, N+C or N-C, where N and C are integers and C represents a preset desired increment of change for the timing signal per strobe, i.e. the fineness of the adjustment of the timing signal. When not strobed by the strobe signal, the state machine produces a count signal of value N.

Abstract: Apparatus is provided for transferring user defined data from a parallel storage medium to a serial link driver in an I/O channel subsystem of a processor or I/O device controller. The serial link driver transmits a frame of user defined data over a serial data transfer medium. A data buffer receives and stores user defined data from the parallel storage medium. A control data facility that is distinct from the data buffer forms and transmits control data from the sender of the frame to the recipient of the frame via a path that does not include the data buffer. The control data facility includes respectively different dedicated logic for asynchronously generating each of the following: special character sequences, frame delimiters, headers, and cyclic redundancy checksums. A switching facility receives the user defined data from the data buffer. The switching facility also receives control data from the control data facility.

Abstract: Disclosed is a telephony messaging transfer system permitting a messaging host to redistribute its processing and/or storage load to another messaging host. An administrator can dynamically control the amount of time needed to transfer specified mailboxes by monitoring the progress on-line and increasing or decreasing the number of transfer dialogs to be used in the transfer process. Also provided is a predictive simulator for simulating the transfer process and providing statistics that can be used to adjust the timing of the actual transfer.

Abstract: A technique for accepting test vectors in one format, generally proven to operate correctly, from an IC tester such as the Logic Master XL2 ("off-bench tester") and processing/converting them into another format for use in a stimulus generator such as the HFS 9009 for bench top testing. The process, which in the exemplary embodiment is implemented in software, accepts various parameters as inputs (e.g., channel name(s) for stimulus generator, range of vectors, etc.) for purposes of extraction and translation. The process provides an Interface and Initialization Unit (IIU) and a Translator Unit (TU). The IIU provides a user interface necessary for a user to select the various options available. In addition, the IIU coordinates the use of memory, file I/O and communication with the active files on the off-bench tester. The IIU verifies user selections and does error checking. Once complete, the TU translates the selected signals for the vector range entered by the user.

Abstract: A video controller that enables applications operating in a protected, multiprocessing system to update a video memory at native speeds. In this system and method, each application is assigned a separate physical address region that identifies an alias of an application's window in the video memory. The separate physical address regions provide an addressing mechanism for an application to identify a referenced set of pixels sought to be accessed. A window mapping function within the video controller that performs only those portions of a video memory access request that references pixels contained within a visible portion of an application's window as defined by priority, size and position information in a control structure.

Abstract: Apparatus and method are provided for adaptively modulating or combining a first signal with a second signal. A series of values of the first signal are taken and sequentially stored in a shift register. The maximum absolute value of the oldest N values (where N is an integer) stored in the shift register is then determined. Before, during or after that determination, the maximum absolute value of the remaining (newer) series of values of the shift register is also determined. The lesser of those two maximum absolute values is then determined. This lesser maximum absolute value is then multiplied by a gain factor representing the desired gain to produce a scale factor. The gain factor can be a preset constant, or can be based on the steady-state ratio of the power of the second signal to the power of the first signal. The second signal is then multiplied by the scale factor to produce a scaled signal.

Abstract: A quiescent test circuit for interfacing a high precision integrated circuit tester to a device under test (DUT). The quiescent test circuit is capable of supplying a high powered (V1) voltage supply to a DUT while the DUT's desired dynamics internal state is reached. At this point, the integrated circuit tester, sends an active select signal to the quiescent test circuit instantaneously which deselects the high-powered (V1) voltage supply to the DUT and selects the integrated circuit tester's parametric measurement unit low power (V4) voltage supply for powering the DUT. The integrated circuit tester, through its parametric measurement unit is capable of precisely measuring the very low quiescent current of the DUT, while powering the DUT.

Abstract: A high speed bit synchronizer is provided with a digital phase detector and a digital offset eliminating circuit. The output of the digital offset eliminating circuit is summed together with the output of the digital phase detector to compensate for the DC offset voltage generated by unsymmetrical digital data received at the input of the phase detector. Further, the phase error offset voltage produced at the output of the digital phase detector is linearized so that the lock point of the phase S-curve located on a linearized portion of a phase offset S-curve, thus, substantially eliminating all seeking and jitter that normally occurs at the lock point.

Abstract: The cooling of a heat generating component mounted outside of the main portion of an enclosure that is cooled using an airstream created by an active air handler is disclosed. The invention is preferably used to cool components such as displays that generate heat, but which are mounted outside the enclosure that houses the main electronics package. The disclosed system, permits inlet air to enter via a vent, and a first duct formed by a baffle routes the inlet air along the back of the displays, removing excess heat. The air is then channeled by a second duct to an area adjacent the enclosure. Since the airstream within the enclosure has created a low pressure area, the passive air stream infiltrates the enclosure and mixes with the main airstream. The disclosed system thus cools the remotely mounted components passively, without requiring additional air handlers or diminishing the pressure and velocity within the enclosure.

Abstract: Apparatus and method for coordinating cache coherency between host cache memories in a distributed information system in a system which comprises at least one main storage memory coupled to a plurality of host computers through controllers. Each host computer includes a host cache controller which maintains the state of the data stored in its associated memory and maintains communicating with a main memory controller for participating in the control of coordinated reading and writing of data between the host cache memories and the main storage memory. The system maintains cache coherency by the exchange of commands between the main memory controller and the hosts cache controllers each of which define the state of the blocks of data stored in the host cache memories.

Abstract: A method for communicating active messages among nodes of a parallel processing computer system is disclosed. The active messages are defined by .mu.threads, and the method comprises the steps of: (a) generating a .mu.thread comprising an instruction pointer, frame pointer, and Local Parameters pointer from a first node to a second node; and (b) performing a procedure on a data structure in accordance with the .mu.thread. The instruction pointer points to an application specific procedure in system memory, and the frame pointer points to an application specific data structure in system memory. The Local Parameters pointer points to one or more words of additional data or parameters stored in memory mapped device registers or system memory.

Abstract: A desktop programmable Graphical User Interface (GUI) workstation that can be easily programmed to perform a custom applications, without the need of text editor. In other words, programming the desktop programmable GUI workstation does not require the program user to utilize a text editor, create or edit code, or understand any particular programming language. The programmer user can program the workstation in an icon environment from predefined functions stored in libraries. Once programmed the workstation employs a GUI which provides an end user with an easy to use and easy to understand interface to their application specific process. The user interface is structured to organize work tasks by major activities of the application specific process. The workstation allows the user to integrate generic window technology such as word processing into their application specific process.

Abstract: A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e.g., multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU.

Abstract: A method is provided for collecting information located within a plurality of hardware elements of a computer system. The hardware elements of the plurality of hardware elements are simultaneously instructed to collect the information. The information within the instructed hardware elements is simultaneously collected. A maintenance system is provided for monitoring the computer system and determining a computer system error in accordance with the monitoring. The step of simultaneously instructing the hardware elements to collect the information is performed in accordance with a computer error determined in this manner. The hardware elements, which may be hardware processors, are provided with individual hardware modules which receive the simultaneous instructions to collect data and direct the simultaneous collection of information within the hardware elements. A transmission link is coupled to each hardware element in the computer system for transmitting the collected information.

Abstract: A low latency software and hardware interface between a microprocessor and Network Interface Unit is disclosed. The Network Interface Unit interfaces to the microprocessor's Level 2 cache interface, which provides burst transfers of cache lines between the microprocessor and Network Interface Unit. The Network Interface Unit is memory mapped into the microprocessor's address space. Two memory mapped cache lines are used to write commands to the Network Interface Unit's Write Window and another two cache lines are used to read results of the commands from the Network Interface Unit's Read Window. The Write Window is a three port register file. Data is written into one write port and read simultaneously from two read ports. One read port is used during read operations to the Write Window while the other is used during command execution to move data to the Internal Structures block. The Read Window is a 2-1 multiplexor that is 128 bits wide.

Abstract: A novel code division multiple access (CDMA) system and apparatus is provided which permits a plurality of encoded modulated data messages to be transmitted simultaneously on the same channel in one frequency band as a composite CDMA signal. An identification signal is generated and spread by a spreading signal having a duty cycle less than fifty percent to produce a combined signal which is transmitted to a receiver having a tapped delay with a plurality of taps each of which produce a replica of the received combined signal delayed by an odd multiple of the duty cycle of the spreading signal. Each of the replica signals is multiplied by a predetermined weighted value to produce weighted delayed signals and a controller responsive to the received combined signal, is employed for controlling individual weighted delayed signals which are then combined to suppress the spreading signal leaving the identification signal.

Abstract: An improved quadrature phase shift key modulator circuit of the type which includes a non-linear amplifier in the transmitter and includes a frequency select logic circuit for receiving the in phase and quadrature phase digital data to be modulated onto a carrier frequency signal. The output of the frequency select circuit produces select signals that are coupled to the input of a digital carrier frequency generator. The digital carrier frequency generator synthesizes and increases, decreases, or leaves unchanged the carrier frequency as a representation of the data occurring on the in phase and quadrature phase input lines. The output of the digital carrier frequency generator is smoothed and converted to an analog signal which has a constant vector power magnitude during phase change.

Abstract: A high speed data transfer mechanism for transferring files from a transmission host across a data link to a receiver host. First, data is presented to a data splitter. The data splitter separates the input data stream into N separate substreams by packaging data into packets, which may be of different sizes. As data is packetized, each packet is sent and presented to a separate data transmitter. Data is sent to the array of transmitter in round-robin fashion such that the data is first presented to the first transmitter, then to the second transmitter, and so on until each transmitter has been sent a packet, then the first transmitter is sent another, and so on, until all data packets have been sent to a transmitter. A receiving side of the mechanism then initializes as many receivers as needed, or as many data receive substreams as are required using as many receivers as are available, ideally an equal number to the transmitters.

Abstract: An improved load board design having a generic test circuit integrated into the load board capable of functioning with varying devices under test and requires little to no wiring. The test circuit is located in a fixed and optimal position of the load board with relation to the DUT. In a preferred embodiment, the test circuit is a quiescent test circuit for interfacing an integrated circuit tester to the DUT. The quiescent test circuit is capable of supplying high powered voltage to a DUT while the DUT's desired internal state is reached. At this point, the integrated circuit tester, sends an active select signal to the quiescent test circuit instantaneously deselecting the high-powered voltage supply to the DUT and selecting the integrated circuit tester's parametric measurement unit for powering the DUT. The integrated circuit tester, through a parametric measurement unit is capable of measuring the quiescent current of the DUT, while powering the DUT.