Patents Represented by Attorney John G. Graham
  • Patent number: 4722075
    Abstract: An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V.sub.BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V.sub.T above V.sub.BIAS. Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V.sub.T about V.sub.BIAS. The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.
    Type: Grant
    Filed: October 15, 1985
    Date of Patent: January 26, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey K. Kaszubinski, David D. Wilmoth, Timmie M. Coffman, John F. Schreck
  • Patent number: 4720819
    Abstract: In a video computer system and the like having a bit-mapped RAM component including a shift register, an improved method is provided for rapidly clearing the RAM in order to prepare the system to receive new input data. More particularly, a preselected number of predetermined data bits corresponding to the number of columns in the RAM is serially shifted into the register. Thereafter, the contents of the shift register are progressively shifted into each of the rows in the RAM until all rows are filled.
    Type: Grant
    Filed: December 30, 1983
    Date of Patent: January 19, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Raymond Pinkham, Karl M. Guttag
  • Patent number: 4720817
    Abstract: A fuse selectable decoder for a redundant row of memory elements in an array includes a redundant decode select circuit (38) for receiving predecoder inputs from predecode lines (28), (30), (32) and (34). The predecode lines are output from predecoders (20), (24) and (26) which decode an eight bit address word. The redundant decode select circuit (38) is programmed by fuse select circuit (40) that selects the address of a defective one of the rows of memory elements in an array (10). The redundant decode select circuit (38) selects one line out of each of the predecode lines (28), (30), (32) and (34) for input to an AND gate (112) for selecting the redundant row (12).
    Type: Grant
    Filed: February 26, 1985
    Date of Patent: January 19, 1988
    Assignee: Texas Instruments Incorporated
    Inventor: Jimmie D. Childers
  • Patent number: 4719355
    Abstract: An ion source of a type used on ion implanters which includes a crucible having a hollow interior and a hole for providing fluid communication between the interior of and exterior to the crucible. A heater assembly is used for adjustably heating the crucible. The crucible hole is if fluid communication with a passageway down the crucible and with a vapor nozzle aperture. An arc chamber has an inlet positioned at the output of the vapor nozzle aperture. The material to be vaporized does not bond to the crucible interior when solidified from a liquid state.
    Type: Grant
    Filed: April 10, 1986
    Date of Patent: January 12, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Victor Meyers, Michael Relue
  • Patent number: 4718041
    Abstract: Disclosed is a method and apparatus for extending the programmable life of an EEPROM memory. For each write commamd generated external to the memory an automatic internal read operation is executed. Each internally generated read operation is accompanied by an increased sense voltage. Data written into selected cells is temporarily stored and compared with the data read. If a match of the compared data is found, the memory operations continue as usual. If a mismatch is found, an internally generated write operation is generated, the programming voltage is increased, and the data temporarily stored is rewritten at the increased voltage. Data polling features are provided with both the internal and externally generated write operations.
    Type: Grant
    Filed: January 9, 1986
    Date of Patent: January 5, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Baglee, Michael C. Smayling
  • Patent number: 4716322
    Abstract: A device for controlling the states of various parts of a main circuit during "power-on" operations which includes an auxiliary circuit for generating a disabling signal when the value of the main circuit supply voltage is below a threshold value for use in disabling the parts of the main circuit.
    Type: Grant
    Filed: March 25, 1986
    Date of Patent: December 29, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Sebastiano D'Arrigo, Giuliano Imondi, Sossio Vergara
  • Patent number: 4715052
    Abstract: A frequency divide by n circuit, where n is an odd number, which includes means for splitting an incoming clock signal of frequency "f" into two non-overlapping complementary clock signals of frequency "f" and a shift register circuit. The shift register circuit is coupled to the signal splitting means and generates an output clock signal of frequency f/n in response to the two complementary clock signals. The output clock signal has a duty cycle equal to ((n-1)/2+D.sub.in)/n where D.sub.in is the duty cycle of the incoming clock signal. The output duty cycle is substantially independent of processing and operating conditions.
    Type: Grant
    Filed: March 10, 1986
    Date of Patent: December 22, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Mark A. Stambaugh
  • Patent number: 4713748
    Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program fitch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program memory may be a RAM and this additional RAM may be configured as either program or data memory space.
    Type: Grant
    Filed: February 12, 1985
    Date of Patent: December 15, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Surendar S. Magar, Daniel L. Essig, Richard D. Simpson, Edward R. Caudel
  • Patent number: 4713749
    Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. A multiplier circuit produces a single state multiply function separate from the ALU. One input to the ALU passes through a full-width shifter with sign extension. The on-chip program memory is a RAM which may be configured as either program or data memory space. The processor may operate will all off-chip program memory and a large on-chip data memory, or with program execution from on-chip RAM (downloaded from the off-chip program memory) using a block move instruction.
    Type: Grant
    Filed: February 12, 1985
    Date of Patent: December 15, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Surendar S. Magar, Daniel L. Essig
  • Patent number: 4710934
    Abstract: A Random Access Memory with error detection/correction capability includes an information array (10) for storage of a collective data word in a single row thereof and a parity array (12) for storage of corresponding parity information in a single row thereof. A single row of the information array (10) and the parity array (12) are accessed and input to an error correct circuit (54). The collective data and parity information are also input to an error syndrome/parity generator (48), the output of which is input to the error correct circuit (54) to correct bits that are in error. A latch (72) is provided for latching the corrected information therein to allow new data to be written therein. The output of the latch (72) is multiplexed into the error syndrome/parity generator (48) which is configurable as a parity generator to generate new parity information for a write operation. The new collective data and parity information in the write mode are stored in arrays (10) and (12).
    Type: Grant
    Filed: November 8, 1985
    Date of Patent: December 1, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Kevin Traynor
  • Patent number: 4710931
    Abstract: A test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n). Each of the functional modules is interfaced with the exterior of the logic circuit with a data bus (20), address bus (16) and a control bus (12). Each of the modules (26) is addressable through an address decode/select circuit (52) to operationally isolate the select modules and define a test boundary. Test data is scanned into a serial chain of shift register latches (SRL's) which are connected in a daisy chain configuration. The defined test boundary allows each of the modules to be separately selected and tested such that the test program for an individual module is separate and distinct.
    Type: Grant
    Filed: October 23, 1985
    Date of Patent: December 1, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey D. Bellay, Theo J. Powell
  • Patent number: 4710933
    Abstract: A testable logic circuit includes parallel registers (72)-(80) for interfacing with a common internal bus (70). The parallel registers (72)-(80) are individually addressable by an address decoder (104) for storage of test vectors therein. These test vectors are then applied to associated logic circuits. Individual shift register latches (92)-(102) are provided at imbedded locations therein. The shift register latches are interfaced with a serial data link to allow serial loading of data therein. The parallel latches function in both the test mode to store test vectors for application to the associated logic and also in the operational mode for storage of logic data. Use of parallel registers increases the speed at which data is scanned into the device.
    Type: Grant
    Filed: October 23, 1985
    Date of Patent: December 1, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Theo J. Powell, Jeffrey D. Bellay, Martin D. Daniels, Yin-Chao Hwang
  • Patent number: 4707626
    Abstract: A delay circuit for internal clock generation in a dynamic RAM uses a one-shot multivibrator composed of a pair of cross-coupled CMOS NOR gates with a RC delay circuit in the coupling path between the output of one NOR gate and the input of the other. The RC delay circuit uses an MOS transistor as the resistor, with the gate of this device connected to the supply voltage, so the resistance varies with changes in the supply. A CMOS inverter stage in the delay circuit has its input connected across the capacitor of the RC delay, so the trip point will vary with threshold voltage. In a dynamic RAM, this circuit may be used to establish the critical timing between write and read mode.
    Type: Grant
    Filed: July 26, 1984
    Date of Patent: November 17, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Shinji Inoue
  • Patent number: 4706011
    Abstract: A circuit for sensing a voltage present on an input line higher than a supply voltage V.sub.DD which includes an isolation switch coupled between the input line and an output line, a threshold adjustment diode coupled in series with the isolation switch also between the input and output lines for establishing a voltage above V.sub.DD at which the isolation switch turns on and a constant current source coupled from an output of the sensing circuit and ground.
    Type: Grant
    Filed: July 7, 1986
    Date of Patent: November 10, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Sossio Vergara, Sebastiano D'Arrigo, Giuliano Imondi
  • Patent number: 4701633
    Abstract: A clock delay circuit of the type used in semiconductor dynamic read/write memory device employs pull-up and pull-down output transistors connected in series between a voltage supply and ground. Excess current in this series path is minimized by a circuit holding the gate of the output pull-up transistor to a low voltage until the gate of the pull-down transistor goes low. Then, the gate of the pull-up transistor is booted above the supply voltage. Also, tendency for the output voltage to rise above ground during the delay period is avoided.
    Type: Grant
    Filed: April 30, 1985
    Date of Patent: October 20, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Jino Chun
  • Patent number: 4701921
    Abstract: A modularized scanned logic test system includes modularized logic circuits (26) having control/observation locations therein. Each of the control/observation locations has a shift register latch (SRL) disposed thereat. A common scan data in line (28) provides data to a serial input to each of the modules (26). The serial output of each of the modules (26) is interfaced with a scan data out line (30). An address on a bus (16) is provided to a decoder (52) to select one of the modules (26). An isolation gate (48) allows for input of data to only the select one of the modules (26) and an isolation gate (50) allows output of data only from the select one of the modules (26) to the scan data out line (30).
    Type: Grant
    Filed: October 23, 1985
    Date of Patent: October 20, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Theo J. Powell, Yin-Chao Hwang
  • Patent number: 4701885
    Abstract: A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a quasi-folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects one of the two segments to be connected to one of the two bit lines. Instead of being interleaved one-for-one, the word lines for cells to be connected to the two bit lines are in groups one group for each segment line; the groups are interleaved. The combined segment line and bit line capacitance has a more favorable ratio to the storage capacitance, compared to the one-for-one interleaved layout.
    Type: Grant
    Filed: July 26, 1984
    Date of Patent: October 20, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: David J. McElroy
  • Patent number: 4700215
    Abstract: A semiconductor integrated circuit has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi.sub.2 or WSi.sub.2. Adhesion of the metal silicide to the polysilicon is enhanced by forming a thin silicon oxide coating on the polysilicon before sputtering the metal silicide. The resulting structure has low resistance but retains the advantages of polysilicon on silicon.
    Type: Grant
    Filed: November 19, 1981
    Date of Patent: October 13, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Joe W. McPherson
  • Patent number: 4698588
    Abstract: A transparent shift register latch (170) includes a normal operating gate (182) and a test gate (184) for selectively connecting data to a node (180). The node (180) is input to an isolation gate (186) through an inverter (188) for connection to an output node (190). A peripheral port (172) is interfaced with the output node (190) through an isolation gate (192). The gates (186) and (192) are operable in a test mode to interface data stored on the node (180) with the output of the latch (170) and inhibit input of data from the port (172). In the normal operating mode, the isolation gate (192) is closed and the isolation gate (186) is opened. The transparent shift register latch (170) allows testing of interface lines between adjacent logic modules.
    Type: Grant
    Filed: October 23, 1985
    Date of Patent: October 6, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Yin-Chao Hwang, Theo J. Powell
  • Patent number: 4696092
    Abstract: A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.
    Type: Grant
    Filed: December 31, 1985
    Date of Patent: September 29, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Robert R. Doering, Gregory J. Armstrong