Patents Represented by Attorney John G. Graham
  • Patent number: 4658377
    Abstract: A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects a segment to be connected to the bit line. The ratio of storage capacitance to effective bit line capacitance is increased, because the bit line itself is of lower capacitance to the substrate.
    Type: Grant
    Filed: July 26, 1984
    Date of Patent: April 14, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: David J. McElroy
  • Patent number: 4658382
    Abstract: A semiconductor read/write memory device of the type using dynamic one-transistor storage cells employs dummy capacitors which are the same size as the storage capacitors, and these dummy capacitors are precharged to a reference voltage level less than half the supply voltage. A voltage divider sets the precharge level, but this divider is shunted by a control device initially so the dummy capacitors are quickly discharged to the reference level. A comparator with differential inputs determines when the reference level has reached the proper value, then the control device and the comparator are shut off to reduce power, and the reference level maintained by the voltage divider. The dummy capacitor precharge starts during the later part of an active cycle, so the specified cycle time can be minimized.
    Type: Grant
    Filed: July 11, 1984
    Date of Patent: April 14, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Bao G. Tran, Hugh P. McAdams, Jimmie D. Childers
  • Patent number: 4656613
    Abstract: A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit lines, and active pull-up circuits for restoring bit lines to a full 1 level. The pull-up circuits are not activated on the dummy cell sides, however, because the power used to restore the dummy cell would be wasted since the dummy cell capacitors are always discharged. The device illustrated uses folded bit lines and multiplexed sense amplifiers; one of two opposite pairs of bit lines is selected. The two opposite pairs share precharge and active pull-up circuits on one side of the array, and share column output lines on the opposite side. The multiplex circuitry selects one side or the other for sensing, and also couples precharge and boost voltages or read/write data back and forth from one side of the sense amplifier to the other.
    Type: Grant
    Filed: August 29, 1984
    Date of Patent: April 7, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Roger D. Norwood, Chitranjan Reddy
  • Patent number: 4656369
    Abstract: A generator circuit for producing a negative bias voltage on a substrate for a semiconductor device employs a multistage on-chip oscillator driving individul charge pump circuits for each stage. The oscillator may produce a frequency related to the value of the negative bias, using a feedback circuit. Each of the charge pump circuits includes a capacitor and an MOS diode coupled to the substrate and another diode coupled to the ground terminal of the supply.
    Type: Grant
    Filed: September 17, 1984
    Date of Patent: April 7, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Perry W. Lou
  • Patent number: 4654827
    Abstract: A semiconductor integrated circuit, such as a high-density, dynamic read/write memory containing an array of rows and columns of memory cells, is constructed to allow high speed testing to identify row line faults in one example, and to identify column or sense amplifier faults in another example. Row lines for the array in a dynamic RAM may contain detector circuits activated in a special test mode to produce a data output indicating integrity of each row line without requiring the access of the cells in the array in complex data patterns. The connection between bit lines in the array and sense amplifiers may be shifted or transposed in another embodiment to distinguish between column or sense amplifier faults; this construction also allows rapid loading of test patterns.
    Type: Grant
    Filed: August 14, 1984
    Date of Patent: March 31, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Jimmie D. Childers
  • Patent number: 4654849
    Abstract: A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.
    Type: Grant
    Filed: August 31, 1984
    Date of Patent: March 31, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Lionel S. White, Jr., Joseph H. Neal, Bao G. Tran
  • Patent number: 4653030
    Abstract: A semiconductor dynamic read/write memory of the multiplexed-address type employs an on-chip refresh counter which is activated by CAS-before-RAS sequence. This counter is made up of stages almost identical to the row address buffers so the same clocks can be used. Either the address input buffers or the refresh counter stages are gated into second-stage row address buffers, and carry feedback from these second stage buffers to the counter stages is used to increment the counter. The access time of the memory for normal read or write is not degraded by the refresh circuitry.
    Type: Grant
    Filed: August 31, 1984
    Date of Patent: March 24, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Tadashi Tachibana, Chitranjan N. Reddy, Ngai H. Hong
  • Patent number: 4651275
    Abstract: A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having a combined on - chip read/write memory for macrocode and microcode storage. A macrocode word is fetched from the memory and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the same memory based on this macrocode word. Both macrocode and microcode may be loaded into the combined memory from external to the chip, so the functions of the microcomputer may be changed for different tasks. The content of both microcode and macrocode, as well as the ratio of macrocode to microcode, can be varied by programming without any change in the circuitry of the chip.
    Type: Grant
    Filed: September 26, 1984
    Date of Patent: March 17, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Kevin C. McDonough
  • Patent number: 4650922
    Abstract: A mounting substrate (10) is formed from a platelet of graphite (22) conformally coated with a layer of silicon carbide (24). A layer of silicon dioxide (25) is disposed thereon and a chip (16) mounted onto the substrate (10). The silicon carbide has a thermal expansion coefficient that is essentially equal to silicon in addition to a high thermal conductivity.
    Type: Grant
    Filed: March 11, 1985
    Date of Patent: March 17, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Joe W. McPherson
  • Patent number: 4648077
    Abstract: A semiconductor memory circuit includes memory arrays (10), (12), (14) and (16). Each of the memory arrays has associated therewith shift registers (34), (36), (38) and (40). Transfer gates (54) are disposed between the memory arrays and the associated shift registers. A control circuit (69) is provided for receiving an external transfer signal and transferring the data between the arrays and the associated shift registers. The shift registers are clocked in response to receiving an external shift clock signal to serially output data therefrom. A delay circuit (292) is provided for delaying shifting of data for a predetermined duration to ensure that a complete transfer of data has been effected. Transfer of data is inhibited until the occurrence of the XBOOT signal by circuit (296) to provide for early occurrence of the transfer signal. Data access is maintained by a delay circuit (330) to accommodate late occurrence of the transfer signal by delaying the internal row address strobe.
    Type: Grant
    Filed: January 22, 1985
    Date of Patent: March 3, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Raymond Pinkham, Fredrick A. Valente, Karl M. Guttag, Jerry R. Vanaken
  • Patent number: 4646232
    Abstract: A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus.
    Type: Grant
    Filed: January 3, 1984
    Date of Patent: February 24, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Ki S. Chang, Michael W. Patrick, Stephen P. Sacarisen, Mark A. Stambaugh
  • Patent number: 4642784
    Abstract: Proven data base is generated for electrical test responses of sporadic defects in integrated circuits as manufactured. Manufactured circuits are subjected to that electrical testing and resulting responses used to identify defect and check the manufacture to avoid its repetition.
    Type: Grant
    Filed: April 26, 1984
    Date of Patent: February 10, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Lionel S. White, Jr., Maury Zivitz
  • Patent number: 4641308
    Abstract: A microprocessor device is used in an adapter for a communications loop of the closed ring, one-way, token-passing local area network type. Each station has a host processor with a host CPU, a main memory, and a system bus, and has an adapter including the microprocessor tested according to the invention. The adapter coupled to the main memory by the system bus and includes a local CPU (the microprocessor), a local read/write memory, and a local bus. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station receives a free token, the transmit-and-receive controller copies the message frame to be transmitted from the local read/write memory to the outgoing signal path, converting from parallel to serial. When a message addressed to this station is received, the controller converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus.
    Type: Grant
    Filed: January 3, 1984
    Date of Patent: February 3, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen P. Sacarisen, Otto N. Fanini
  • Patent number: 4639890
    Abstract: In a computer system, an improved memory circuit is provided for accomodating video display circuits with CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accomodate any CRT screen intended to be used, and it further includes a serial shift register having a plurality of taps at locations corresponding to different preselected columns of cells in the chip. In the system, provision is included for selecting taps to unload only the portion of the shift register containing the bits of interest, whereby unused portions of the chip may be effectively excluded and the time for transferring data of interest to the CRT screen is reduced.
    Type: Grant
    Filed: December 30, 1983
    Date of Patent: January 27, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew Heilveil, Jerry R. VanAken, Karl M. Guttag, Donald J. Redwine, Raymond Pinkham, Mark F. Novak
  • Patent number: 4638182
    Abstract: A CMOS driver circuit for producing a high-level voltage, exceeding the voltage supply, uses an inverter and an output stage. The inverter circuit is supplied from the usual voltage supply for the chip, and this inverter is followed by the output stage which is supplied from an on-chip generator producing a higher level voltage. The current requirement of the on-chip generator is kept to a minimum by charging the output capacitance mainly from the voltage supply, and using the output stage only for the latter part of a charging cycle.
    Type: Grant
    Filed: July 11, 1984
    Date of Patent: January 20, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Hugh P. McAdams
  • Patent number: 4638451
    Abstract: A microprocessor system includes a CPU device with on-chip or off-chip memory, and data and control busses for accessing memory and/or peripherals. The peripheral circuitry includes one or more channels for input and/or output of data, wherein various characteristics of the treatment of data in the channel are controlled by the program being executed in the CPU. In one embodiment analog input and output channels are included, and the A-to-D or D-to-A conversion rates are selected by executing a data output instruction by the CPU. The cut-off points of the filters are likewise selected. The A-to-D converter loads a first-in first-out memory which is read by the CPU in burst mode when filled. Likewise, the CPU loads digital data to a first-in first-out memory in the output channel, and then the D-to-A converts at its selected rate.
    Type: Grant
    Filed: May 3, 1983
    Date of Patent: January 20, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Richard K. Hester, Khen-Sang Tan
  • Patent number: 4636657
    Abstract: A -CMOS clock generator circuit is controlled by two clocks, one always going high before the other when entering an active cycle, and always going low before the other in entering a precharge cycle; this one clock precharges a capacitor through a P-channel transistor, and holds a drive node discharged. Two sets of semi-connected N-channel output transistors are used, with the gates of the top two driven by the drive node, and the gates of the bottom two driven by a CMOS inverter which has the second clock as its input. The inverter output also drives the gate of a P-channel transistor between the capacitor and the drive node. Another P-channel transistor with the first clock on its gate couples the drive node to the intermediate node of the first output pair. The second clock transfers the charge from the capacitor to the drive node, which also causes the capacitor to boot the drive node above the supply. When the first clock goes low it discharges the booted node to the supply rather than to ground.
    Type: Grant
    Filed: August 29, 1984
    Date of Patent: January 13, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Chitranjan Reddy
  • Patent number: 4636987
    Abstract: A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit line halves which are of the folded type. The sense amplifiers are multiplexed so that one of two opposite pairs of bit line halves are selected. The two opposite pairs share precharge and active pull-up circuits on one side of the array, and share column output lines on the opposite side. Thus, the multiplex circuitry operates not only for selecting one side or the other for sensing, but also for coupling precharge and boost voltages or read/write data back and forth from one side of the sense amplifier to the other. The active pull-up circuits are activated in both read and write portions of a read-modify-write cycle.
    Type: Grant
    Filed: August 29, 1984
    Date of Patent: January 13, 1987
    Assignee: Texas Instruments
    Inventors: Roger D. Norwood, Chitranjan Reddy
  • Patent number: 4636986
    Abstract: A circuit for inhibiting data transfer to addressed memory locations in a plurality of arrays on a semiconductor chip includes an arbitration circuit (68) that distinguishes between separate inhibit signal inputs on dedicated CAS terminals and multiplexed inhibit signals on the input of an I/O buffer (66). The arbitration circuit (68) controls the enable circuits (64) for transferring data from the I/O buffer (66) to memory arrays (10), (12), (14) and (16). Separate inhibit signals allow multiple arrays to share common row and column decoders and maintain separate read/write capability.
    Type: Grant
    Filed: January 22, 1985
    Date of Patent: January 13, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Raymond Pinkham
  • Patent number: 4634901
    Abstract: A sense amplifier circuit for a CMOS DRAM or the like uses cross-coupled P-channel load transistors and cross-coupled N-channel driver transistors. Both of the P-channel transistors are in an N-well in the center of a symmetrical layout on the chip. Each N-channel transistor is split into two separate transistors, one on each side of the N-well, so that a balanced configuration is possible.
    Type: Grant
    Filed: August 2, 1984
    Date of Patent: January 6, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: David J. McElroy