Abstract: The disclosed is a read only memory having a plurality of memory blocks each associated with main bit lines and sub-bit lines, and a plurality of memory cells for storing information, and sense amplifiers for reading the information stored in the memory cells through the main bit lines. The memory also has a block selection part disposed between the blocks and having a plurality of block selection transistors connecting the main bit lines to the sub-bit lines. The sub-bit lines elongate to at least an adjacent block and alternatively connected to the main bit lines through the block selection part.

Abstract: A method of fabricating a semiconductor device where the formation of a conductive layer typically over a storage capacitor on the device is used both as a plate electrode and also as an interconnect line. The method therefore combines the fabrication process steps of forming a plate electrode with the steps of forming a wiring layer. In a preferred embodiment, the storage capacitor is part of a cell array portion of a semiconductor memory device, whereas the interconnect line is in a peripheral portion of the memory device.

Abstract: A method of forming an interconnection by using a landing pad is disclosed. In a semiconductor device having a memory cell portion and a peripheral circuit portion, a refractory metal is used for the bitline instead of the usual polycide, to concurrently form a contact on each active region of an N-type and a P-type, then a landing pad is formed on the peripheral circuit portion when a bitline is formed on the memory cell portion. In such a process, a substantial contact hole for the interconnection is formed on the landing pad so that an aspect ratio of the contact can be lowered. Accordingly, when forming a metal interconnection, the contact hole for the interconnection is easily filled by Al reflow so that the coverage-step of the metal being depositing in the contact hole for the interconnection is enhanced, the contact resistance is reduced. Further, the reliability of the semiconductor device is improved.

Abstract: A method for manufacturing a transmission electron microscope analysis sample of a substrate containing an insulating body or an insulating sample includes the steps of: depositing a conductive material on the sample and then polishing the sample using a focused ion beam. The polishing step removes the conductive material from the analysis point of the sample, such that an electron projection and transmission path is formed through the sample at the analysis point. However, the conductive material is not removed from the remainder of the sample, not including the analysis point, thereby forming a ground path for any charges formed in the sample.

Abstract: A semiconductor device includes a source and a drain formed in a device region of a semiconductor substrate, and an electrode withdrawal portion having an impurity concentration higher than that of the device region. The electrode withdrawal portion is formed so as to adjoin either one of the source and drain. An electrode for the source or drain adjacent to the electrode withdrawal portion is used jointly as an electrode for the electrode withdrawal portion.

Abstract: In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.

Abstract: A volatile memory initialization systems differentiates between a first class of reset causes requiring memory initialization and a second class of reset causes not requiring memory initialization. A register records the first and second classes of reset causes. A volatile memory initialization function is performed when a reset of the first class of reset causes is read from the register. The volatile memory initialization function is bypassed when a reset of the second class of reset causes is read from the register.

Abstract: Of ends of a plurality of inner leads disposed around a semiconductor chip shaped substantially in the form of a rectangle, the ends of the inner leads, which correspond to the corners of the rectangle, are provided so as to approach in the direction of the semiconductor chip. Owing to the provision referred to above, bonding wires for connecting electrical connections between the semiconductor chip and the ends of the inner leads can be prevented from drifting upon a mold process.

Abstract: In a method for manufacturing a dielectric isolation substrate according to the present invention, during the process of pressing a semiconductor substrate (wafer), a dummy chip 103 is positioned toward the outside edge of the wafer with respect to the LSI chip 102, which is pressed into contact last, V-grooves 103A in the dummy chip 103 are formed to be deeper than V-grooves 102A in the LSI chip 102 so that voids can be effectively pushed into the dummy chip 103. Consequently, isolation of the LSI chip caused by voids can be prevented, thereby achieving an improvement in yield.

Abstract: A method for determining a position of track-0 and mapping tracks according thereto is disclosed. In a method for mapping tracks of a disk drive apparatus which uses a multiplatter system and stores track-0 information in a maintenance region, a head on a platter including track-0 is switched to sequentially search tracks along the surface of the platter from the track-0. When the head is positioned at an outer track or an inner track during track search, the head is switched to sequentially search tracks of the selected platter, and the track search for all the platters of multiple platters is repeated.

Abstract: In a process where a capacitor using a BST film for a dielectric film is incorporated into a DRAM, the film is selectively removed by wet etching for forming a contact hole. For this purpose, a bottom electrode is formed and then an amorphous film is formed on the entire surface of a silicon wafer. And after forming a crystalline top electrode on this film, lamp heating is performed to crystallize only the area that is in contact with the electrode. Then wet etching is performed using a solution of hydrogen and ammonium fluoride (1:2), which allows removing only the amorphous area selectively.

Abstract: The present invention discloses a method for making a dynamic random access memory by silicon-on-insulator comprising the steps of: dividing a cell area and a peripheral area on a first silicon substrate and recessing just the cell area where a memory device is formed; forming a first insulating layer by isolation of electrical elements in order to divide an active region and a passive region; forming and patterning a first conductive layer through a contact to which the active region and a capacitor are connected on the insulating layer to form a storage node; forming a dielectric layer of the capacitor on the storage node; forming and patterning a polysilicon layer on the dielectric layer to form a storage node; forming a second insulating layer on the plate node and planarizing the insulating layer by thermal treatment; forming a third conductive layer to a predetermined thickness on the planarized insulating layer; polishing and planarizing the third conductive layer by chemical-mechanical polishing techn

Abstract: A semiconductor device package is equipped with devices for preventing the formulation of air traps in its encapsulated package body. These devices include dummy block leads formed on the outermost inner lead of each row of inner leads, and extended portions formed on each tie bar. Each dummy block lead extends from the end of an outermost inner lead and is integrally formed therewith. The tie bar extended portions are separated into several parts defined by spaces between the parts, and the several parts are formed integral with each other and with the tie bar. The dummy block leads and the tie bar extended portions may be formed so as to be inclined relative to horizontal and with jagged edges at their side surfaces. The dummy block leads and tie bar extended portions serve to reduce the velocity of the potting resin which forms the encapsulate, as it enters the die cavity for encapsulation, but before the resin actually contacts the chip or the inner leads.

Abstract: A semiconductor chip comprises a plurality of bonding pads formed in a row along an edge of the chip and spaced at a designated gap pitch between confronting sides of adjacent pads. Each of the pads has a length perpendicular to the edge of the chip, a length distance, a width parallel to the edge of the chip, and a width distance. The length distance is different than the width distance.

Abstract: The present invention is a technique of, and system for, imaging vascular anatomy over distance considerably greater than the maximum practical field of view of a magnetic resonance imaging system while using substantially one contrast agent injection. The technique and system of the present invention acquires image data of a plurality of image volumes which are representative of different portions of the patient's body. The image data of each image volume includes image data which is representative of the center of k-space. The acquisition of image data which is representative of the center of k-space is correlated with a concentration of contrast agent in the artery(ies) residing in the image volume being substantially greater than the concentration of contrast agent in veins and background tissue adjacent to the artery(ies).

Abstract: A selective oxidation process includes conducting a former phase of an oxidation process employing a thick mask layer to produce an oxide layer having a thickness less than the finished thickness of a desired semiconductor device isolation insulator. Then the thickness of the mask layer is reduced and a latter phase of the oxidation process using the reducing thickness mask layer is performed to produce the desired semiconductor device isolation insulator having the ultimate thickness. The use of both a thick mask layer and a reduced thickness mask layer for various phases of the oxidation process limits both the growth of the bird's beak and the growth of crystalline defects in the bird's beak.

Abstract: A CMOS output buffer circuit includes a predriving circuit which generates two predriving signals, a main driving circuit which has a plurality of parallel connected pull-up transistors and a plurality of parallel connected pull-down transistors, and a sequential driving circuit which provides sequential pull-up and pull-down driving signals to the pull-up and pull-down transistors, respectively. The main driving circuit generates the output signal according to the sequential pull-up or pull-down driving signals, whereby the output signal is developed step by step into either the power supply potential or the ground potential. In the manner, any spike in the switching current is considerably mitigated, thereby reducing switching noise.

Abstract: An improved wafer boat for a vertical furnace has inner upper and lower corners formed as sloped surfaces, and has outer upper and lower corners formed as sloped surfaces. This prevents the formation and collection of particles off of the wafer boat that can generate a protrusion on the wafer boat. By preventing the formation of a protrusion, this improved wafer boat prevents damage to the wafers processed in the wafer boat and improves the reliability of semiconductor devices formed from those wafers. Also, holes are provided for locking pins on both the upper and lower plates of the wafer boat. This means that the wafer boat can be loaded into the furnace in both a rightside-up and upside-down orientation, thus increasing the lifespan of the boat and reducing boat maintenance costs.

Abstract: A gray code decoding circuit of a hard disk drive includes a servo pattern area, a data pick-up device, and a pattern detecting device. The servo pattern area has data recorded as a gray code. The data pick-up device detects the recorded data, converts it into encoded read data, and outputs the encoded read data. The pattern detecting device detects a position of the servo pattern area in response to the encoded read data and outputs a reference pulse. The gray code decoding circuit also contains a gray window generating device, a synchronous signal generating device, a gray code extracting device, and a gray-binary converting device. The gray window generating device divides the encoded read data by a division ratio, converts the divided encoded read data into gray data, outputs the gray data, and generates a first synchronous signal after counting by a system clock to a first value. The synchronous signal generating device outputs first and second window signals in response to a second synchronous signal.

Abstract: A negative pressure air bearing slider includes a slider body for flying above a surface of a recording disc during relative rotation of the recording disc. First and second projections extend from a lead portion of a principal surface of the slider body to define first and second air bearing surfaces, respectively, the first and second air bearing surfaces being spaced apart from each other in the lateral direction of said slider body. A third U-shaped projection extends from the principal surface and includes a curved front wall portion at least partially located between the first and second projections and first and second side wall portions extending from opposite ends of the curved front wall portion to a rear portion of the principal surface so as to define a rounded negative pressure cavity therein.