Abstract: A mechanical assembly includes an arm and an extension link that rotate about a pivot point, a yoke, and a force generating device. The yoke includes a first slot in which a pin of the link resides. The yoke translates in a plane responsive to rotation of the counterbalance extension link pin about the pivot point. The force generating device is connected between the counterbalance extension link pin and a fixed point on the yoke to exert a force on the counterbalance extension link pin. The orientation and magnitude of the force produced by the force generating device remains constant as the yoke translates. The force generating device and extension link produce a torque that is equal and opposing to the torque produced by the force of gravity acting on the arm so that the arm is in static equilibrium. The static equilibrium condition is independent of the rotational position of the arm.

Abstract: A fractional N synthesizer is disclosed. The synthesizer includes a phase detector that receives first and second input signals and generates a pulse width modulated (PWM) output signal having a pulse width indicative of the phase relationship between the input signals. A pulse-width-to-amplitude (PW/A) conversion circuit connected to a loop filter where the conversion circuit receives the phase detector output signal and generates a PW/A output signal having an amplitude indicative of the phase detector output signal pulse width. The phase detector output signal may comprise a periodic series of pulses having varying pulse widths and the PW/A output signal amplitude changes at the end of each pulse to reflect the corresponding pulse width. The conversion circuit may include a current circuit connected to a capacitor, where the current signal receives the phase detector output and sources a constant current during a charging phase of the phase detector output signal.

Abstract: A method and system for specifying a targeted device by its network address and inducing the targeted device to produce a user detectable action are disclosed. Initially, an echo locator is invoked by the user at a first device (the initiating device), such as by entering a predetermined keyboard sequence. Upon invoking the locator, the targeted device is then specified by the user with an IP address, a host name, or with some other suitable identifier. If the targeted device is specified indirectly, the locator determines the network device that is associated with the specified device. Once the targeted devices has been identified, the locator of the user device issues one or more messages such as ICMP echo requests that generate a response from the targeted device. In one embodiment, the echo requests do not produce a response unless a threshold number of locator requests are detected within a predetermined time limit.

Abstract: A system and method for handling processor internal errors in a data processing system. The data processing system typically includes a set of main microprocessors that have access to a common system memory via a system bus. The system may further include a service processor that is connected to at least one of the main processors. In addition, the system includes internal error handling hardware configured to log and process internal errors generated by one or more of the main processors. The internal error hardware may include error detection logic configured to receive internal error signals from the main processors. In response to receiving one or more IERR signals, the error detection logic is configured to assert and error detected signal that is received by error logging logic. The error logging logic is configured to update one or more error status register when the error detected signal is asserted.

Abstract: A connection assembly comprising a receptacle portion and a probe portion. The receptacle portion is suitable for attaching to an adapter card. The receptacle may include a cylindrical housing with a longitudinal axis oriented perpendicular to the plane of the card. The receptacle includes a set of contact structures that extend within the interior of the receptacle housing. The set of contact structures are embedded within an electrically insulating contact block and preferably define one or more lines of contact structures extending perpendicularly to the plane of the adapter card. Each contact structure is electrically connected to a corresponding cable or wire. The probe portion may include a probe cover and a probe body configured to be received within the probe cover. The probe cover preferably comprises first and second elements that are separated by a gap that extends parallel to the longitudinal axis of the receptacle.

Abstract: A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.

Abstract: A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode (116) over a gate dielectric (104) over a semiconductor substrate (102). A spacer film (124) exhibiting a tensile stress characteristic is deposited over the gate electrode (116). The stress characteristics of at least a portion of the spacer film is then modulated (132, 192) and the spacer film (124) is etched to form sidewall spacers (160, 162) on the gate electrode sidewalls. The spacer film (124) is an LPCVD silicon nitride in one embodiment. Modulating (132) the spacer film (124) includes implanting Xenon or Germanium into the spacers (160) at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant (132) may be performed selectively or non-selectively either before or after etching the spacer film (124).

Abstract: A microprocessor, data processing system, and method are disclosed for handling parity errors in an address translation facility such as a TLB. The microprocessor includes a load/store unit configured to generate an effective address associated with a load/store instruction. An address translation unit adapted to translate the effective address to a real address using a translation lookaside buffer (TLB). The address translation unit includes a parity checker configured to verify the parity of the real address generated by the TLB and to signal the load store unit when the real address contains a parity error. The load store unit is configured to initiate a TLB parity error interrupt routine in response to the signal from the translation unit. In one embodiment, the TLB interrupt routine selectively invalidates the TLB entry that contained the parity error. The load/store unit preferably includes an effective to real address table (ERAT) containing a set of address translations.

Abstract: A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.

Abstract: A method for forming a sacrificial layer (30) over patterned structures (28) to allow structures (28) to be trimmed laterally without incurring much loss vertically. Structures (28) are patterned on a first layer (26) of a substrate (24). Thereafter, sacrificial layer (30) is deposited on structures (28). During this deposition, the thickness of sacrificial layer (28) grows vertically above structures (28) faster than it grows laterally adjacent to the structures' sidewalls. Sacrificial layer (30) and patterned structures (28) are then etched where the etch rate uniformity ensures that the sacrificial layer (30) covering the sidewalls is cleared before the sacrificial layer covering the horizontal portions thereby enabling etching of the patterned structure sidewalls without reducing the patterned structure height. The sacrificial layer may comprise a polymer formed with a low energy fluorocarbon plasma while the subsequent etch may employ an oxygen plasma.

Abstract: This invention is comprised of a data processing system containing at least one main processor connected to a system bus, a system memory connected to the system bus and accessible to each of the main processors, a tamper mechanism, and a local service processor. The tamper mechanism is configured to change state each time the system is inserted into a slot in a rack enclosure. The local service processor is connected to the tamper mechanism and configured to update an insertion log upon detecting a change in state of the tamper mechanism. The insertion log provides a count and a history of rack insertions to which the system has been subjected. The system may include a non-volatile storage element which is updated exclusively by the local service processor that contains the insertion log. The insertion log may include an insertion counter. In this embodiment, the local service processor is configured to increment the insertion counter upon each insertion.

Abstract: A method and system for responding to requests for static web documents including saving the response as a packet train comprising one or more IP compliant packets. Upon a subsequent request for the static web document, the saved packet train may be retrieved and the header information updated. In this manner, the network protocol processing required to respond to the request is reduced. The server may include code for determining whether a referenced web object is a static object and a directory of recently accessed static web objects and a copy of the corresponding packet trains. The web server may be configured to consult the directory to determine if an object is a static object that has been recently accessed. If the object has been recently accessed, the server may retrieve the corresponding packet train from its system memory or from disk and update the packet headers prior to transmission.

Abstract: A system and method for monitoring the software configuration of a computer system. As a preliminary step in an error recovery procedure initiated in response to detecting a system error condition, it is determined whether one or more configuration files on the system are in an unauthorized state. If so, one embodiment of the invention contemplates suspending the error recovery procedure until the configuration file has been restored to an authorized. In one embodiment, the determination of whether a configuration file is in an unauthorized state is facilitated by associating a configuration file fingerprint with the configuration file where the fingerprint is indicative of the contents of the configuration file. In this embodiment, the contents of the configuration file can be verified against the fingerprint to determine if any unwarranted or unauthorized modifications have been made to the configuration since the fingerprint was generated.

Abstract: A data processing network and an associated method of transmitting protocol data units (PDU) is disclosed. The network includes a first server including a first network interface card (NIC) that connects the first server to a central switch. The network further includes a second server including a second network interface card (NIC) that connects the second server to the central switch. The first NIC is configured to store a first PDU in a buffer upon determining that the first PDU is of a first type and to combine the first PDU stored in the buffer with a second PDU of a second type upon determining that the first and second PDU share a common target. The combined PDU is then forwarded to the common target as a single PDU thereby reducing the number of PDUs traversing the network.

Abstract: A semiconductor fabrication process is disclosed wherein a first gate (108, 114) is formed over a first portion of a semiconductor substrate (102) and a second gate (114, 108) is formed over a second portion of the substrate (102). A spacer film (118) is deposited over substrate (102) and first and second gates (108, 114). First spacers (126) are then formed on sidewalls of the second gate (114) and second spacers (136) are formed on sidewalls of first gate (108). The first and second spacers (126, 136) have different widths. The process may further include forming first source/drain regions (128) in the substrate laterally disposed on either side of the first spacers (126) and second source/drain regions (138) are formed on either side of second spacers (136). The different spacer widths may be achieved using masked first and second spacer etch processes (125, 135) having different degrees of isotropy.

Abstract: A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.

Abstract: A data processing network in which console interactions are communicated to and from server appliances over the network. The system may include a server appliance configured to re-direct serial port transactions to a network port. The service appliance may include a mechanism for transmitting and receiving console data and control information via the network. The system further includes a console server for accepting and displaying console traffic that is sent over the network by a server appliance and for transmitting commands entered by a user back to the server appliance for processing.

Abstract: A system comprising a cluster of diskless servers employing a distributed shared memory abstraction that presents an area of shared memory for two or more processes executing on different servers in the cluster. The invention provides the appearance of a shared memory space between two or more processes thereby potentially reducing disk latency or eliminating redundant computation associated with conventional server clusters. The DSM abstraction may be dynamically alterable such that selectable groups of processes executing on the cluster share a common address space temporarily. The shared memory spaces may be determined empirically or servers may subscribe to a group reactively in response to client requests. Multiple groups may exist simultaneously and a single server may belong to more than one group. The types of objects to which the abstraction is applied may be restricted. Shared memory may be restricted, for example, to read-only objects to alleviate consistency considerations.

Abstract: A flip-flop circuit that includes a set of three p-channel connectors connected in parallel between a supply voltage (Vdd) and a first control node. The circuit further includes three n-channel transistors connected in series between the first control node and Vss. The first control node controls the gate of a p-channel transistor connected between Vdd and an output node. A set of n-channel transistors is connected between the output node and ground. The gates of these transistors are controlled by the clock signal, a delayed clock signal, and an inverted copy of the data signal, which is provided, via a control inverter, to a second control node. The first control node drives the output node to a first state and the second control node drives the output node to a second state. The first and second control nodes are preferably decoupled.

Abstract: A sphere mode texture coordinate generator circuit for use in a graphics adapter of a data processing system is disclosed. The circuit includes a set of input multiplexers configured to receive x, y, and z components of a normal vector and a unit vector corresponding to the current vertex. The circuit further includes a set of functional units such as a floating point multiplier, a floating point adder, a floating point compare-to-zero unit, and an inverse square unit. The functional units are configured to receive outputs from the set of multiplexer and are enabled to perform floating point operations on the outputs of the set of multiplexers. A controller or state machine of the circuit is enabled to determine the state of select inputs to each of the set of multiplexers. The controller manages the multiplexer select inputs such that the circuit determines sphere mode texture coordinates in response to receiving the normal vector and the unit vector.