Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal.

Abstract: A method for allocating memory in a data processing system in which a configuration table indicative of the system's physical memory is generated following a boot event. The configuration table is then modified to identify a portion of the system's physical memory thereby hiding the remaining portion from the operating system. Subsequently, a memory allocation request is initiated by an application program. A device driver invoked by the application program then maps physical memory from the hidden portion to the application's virtual address space to satisfy the application request. The application program may be executing on a first node of a multi-node system in which each node is associated with its own local memory, In this embodiment, the node on which the allocated physical memory is located may be derived from the allocation request thereby facilitating application level, allocation of specified portions of physical memory.

Abstract: A design verification system comprising a set of modular verification engines invoked by a framework that manages the control flow between the engines. The framework receives a verification problem from an application and attempts to solve it by instantiating one or more engine in a customizable sequence or set of sequences. Each verification engine is configured to achieve a specific verification objective and may be coded against a common API to facilitate exchange of information between the engines. The verification engines may include reduction engines, which attempt to simplify a problem by modifying it or decomposing it, and decision engines, which attempt to solve problems that are passed to them. As a verification problem is passed from one engine to the next, the engine may alter the verification problem such that a decision engine at the end of the sequence may receive a verification problem that is simpler to solve than the original problem specified by the system user.

Abstract: A processor, data processing system, and a related method of execution are disclosed. The processor is suitable for receiving a set of instructions and organizing the set of instructions into an instruction group. The instruction group is then dispatched for execution. Upon executing the instruction group, instruction history information indicative of an exception event associated with the instruction group is recorded. Thereafter, the execution of the instruction is modified responsive to the instruction history information to prevent the exception event from occurring during a subsequent execution of the instruction group. The processor includes a storage facility such as an instruction cache, an L2 cache or a system memory, a cracking unit, and a basic block cache. The cracking unit is configured to receive a set of instructions from the storage facility. The cracking unit is adapted to organize the set of instructions into an instruction group.

Abstract: A semiconductor fabrication process and structure in which a semiconductor channel structure (140) having first and second major surfaces perpendicular to a semiconductor substrate (102) is formed overlying and electrically isolated from the substrate (102). First and second gate dielectrics (120, 142) are formed on the channel structure's first and second major surfaces respectively. First and second gate dielectrics (120, 142) differ in at least one characteristic. First and second gate electrodes (116, 152) are formed in contact with the first and second gate dielectrics (120, 142) respectively. The first and second gate electrodes (116, 152) differ in at least one characteristic. First and second gate dielectrics (120, 142) may have different dielectric constants while first and second gate electrodes (116, 152) may have different doping and conducting properties.

Abstract: A system and method for synchronizing a set of nodes connected to a central switch in a multi-node data processing system, such as a NUMA data processing system, are disclosed. Initially, time base register values are retrieved from each of the set of nodes. A common time base register value is then determined based upon the time base register values received from the nodes. The common time base register value that is determined is then broadcast to each of the nodes. Prior to reading the time base register values, packet traffic among the set of nodes may be halted by broadcasting a halt traffic packet to each of the nodes. In this embodiment, normal packet traffic may be resumed after synchronization by broadcasting a resume traffic packet to each of the nodes. The time base register values may be read by issuing a special purpose interrupt from a node adapter to one of the node processors in response to the adapter receiving a read time base packet from the switch.

Abstract: A normalization circuit suitable for use in a graphics adapter is disclosed. The circuit is configured to receive vertex data and includes a set of multiplexer circuits, a set of functional units, and a control circuit. The outputs of the set of multiplexer circuits provide inputs to the set of function units and the control circuit is configured to control the select inputs of the set of multiplexer units to calculate a unit normal vector and a unit eye vector from the received vertex data. The set of functiontional units may include a pair of floating point multipliers and a floating point adder. The inputs of the first floating point multiplier may be connected to outputs of first and second mulitplexers such that the first multiplier is enabled to generate square values for x, y, and z components of the vertex data. The inputs of the floating point adder may be connected to outputs of third and fourth multiplexers, wherein the floating point adders is enabled to generate a sum of squares values.

Abstract: A floating point exponentiation circuit suitable for calculating the value BE is disclosed where B and E are floating point values. The floating point exponentiation circuit includes circuitry for producing a value P, where P is approximately equal to E*((BEXP−127)+log2(1.BMAN), BEXP is an exponent field of the base B, and 1.BMAN is a 24-bit mantissa field of the base B. The floating point exponentiation circuit further includes circuitry for adjusting the value P wherein the floating point representation of the adjusted value of P includes a mantissa field that indicates an integer portion Pi of P and a fractional portion Pf of P.

Abstract: A method and system for transmitting video data are disclosed. The method includes receiving a first video image and comparing the first video image to at least one stock image where each of the stock images is associated with a corresponding index value. If a match between at least a portion of the first video image and one of the at least one stock images is detected, the index value corresponding to the matching stock image is transmitted over a transmission medium. In one embodiment, the method further includes receiving the transmitted index value and generating the corresponding stock image from the index value. The method of may further includes comparing the first video image with a set of stock images. If it is determined that the first image does not match to any of the set of stock images, then a new index value is assigned to the first image and the first image is added to the set of stock images.

Abstract: A microprocessor and method of processing instructions therein are disclosed. Initially, a sequence of instructions is dispatched by a dispatch unit of the microprocessor. A code sequence recognition unit (CSR) is configured to detect a short branch sequence within the sequence of instruction, where the short branch sequence includes a condition setting instruction, a conditional branch, and at least one additional instruction that is executed if the conditional branch is not taken. The short branch sequence is then internally converted to a predicated instruction sequence that includes the condition setting instruction and a predicated instruction corresponding to each additional instruction in the short branch sequence. The predicated instruction sequence is then executed in at least one functional unit of the processor.

Abstract: A system in which bus signals are selectively modified to effectively isolate desired bus agents from the bus. The selective modification of bus signals may be determined from a stored table (permission table) indicating permitted and prohibited bus transaction initiator/target pairs. The permission table may be located in a dedicated device, such as a programmable logic array or application specific integrated circuit. Alternatively, the permission table may be integrated into the bus arbiter. The permission table may be used to provide a unique 1-bit signal to each bus agent indicating whether the corresponding bus agent is permitted to receive transactions from the current bus master. The permission bit may be routed to external gating circuitry associated with each bus agent. The gating circuitry may receive one or more bus control signals and may modify the control signals depending upon the state of the permission bit.

Abstract: A bidirectional bus and data processing system suitable for suppressing cross talk noise are disclosed. The bidirectional bus includes, a first interconnect line driven by a pair of drivers, a first pair of impedance elements connected between the first line and a second line of the bus, and a second pair of impedance elements connected between the first line and a third line of the bus. In one embodiment, the capacitive coupling per unit length between the first line and the second line is approximately equal to k and the impedance of the first pair of impedance elements is approximately equal to (&ugr;k)−1, where &ugr; is the speed of light through a dielectric in which the first and second lines are located. In one embodiment, the impedance of the first driver is approximately equal to (&ugr;c0)−1, wherein c0 is the self-capacitance of the first line.

Abstract: A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline.

Abstract: A method, processor, and data processing system implementing a delayed reject mechanism are disclosed. The processor includes an issue unit suitable for issuing an instruction in a first cycle and a load store unit (LSU). The LSU includes an extend reject calculator circuit configured to receive a set of completion information signals and generate a delay value based thereon. The LSU is adapted to determine whether to reject the instruction in a determination cycle. The number of cycles between the first cycle and the determination cycle is a function of the delay value such that reject timing is variable with respect to the first cycle. In one embodiment, the processor is further configured to reissue the instruction after the determination cycle if the instruction was rejected in the determination cycle. The delay value is conveyed via a 2-bit bus in one embodiment. The 2 bit bus permits delaying the determination cycle from 0 to 3 cycles after a finish cycle.

Abstract: A floating point inverse square root circuit is disclosed. The circuit is configured to receive a floating point value comprised of a sign bit, an exponent field, and a mantissa field. The inverse square root circuit includes a lookup table configured to receive at least a portion of the floating point value and further configured to generate an initial approximation (x0) of the inverse square root of the floating point value from the received portion of the floating point value. The inverse square root circuit further includes a first estimation circuit that receives the initial approximation from the lookup table and at least a portion of a value L derived from the floating point value mantissa field (M) and further configured to produce a first approximation (x1) of the floating point value's inverse square root based upon L and x0 where x1 is a more accurate estimate of the inverse square root than x0.

Abstract: A method, system, and computer program product for generating test sequences are disclosed. Initially, a graphical user interface is invoked to display a list of preexisting test cases. A first test case is selected from the list of test cases and to create a first instance of the first test case, which is added to the test sequence. The test sequence is displayed in a test sequence portion of the graphical user interface. A subsequent test case is then selected from the list of test cases to create an instance of the subsequent test case, which is also added to the test sequence. The GUI may permit the modification of a parameter of the first test case by invoking a test case editor from the GUI. In one embodiment, the subsequent test case and the first case are the same such that first and second instances of the first test cases are included in the test sequence.

Abstract: A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus. A first I/O adapter, which generates 32-bit addresses, is coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table, that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes an Access Control Table (ACT). The ACT determines whether DMA access to the address generated by the 64-bit I/O adapter is authorized.

Abstract: A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.

Abstract: A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die.

Abstract: An integrated circuit verification method and system are disclosed. The method includes generating a test description comprising a set of test cases. The functional coverage achieved by the test description is then determined. The functional coverage achieved is then compared against previously achieved functional coverage and the test description is modified prior to simulation if the test description achieves no incremental functional coverage. In one embodiment, generating the test description comprises generating a test specification and providing the test specification to a test generator suitable for generating the test description. In one embodiment, the test description comprises a generic test description and the generic test description is formatted according to a project specification and simulation environment requirements. If the coverage achieved by the test description satisfies the test specification.