Abstract: In a NPN transistor electrostatic discharge (ESD) protection structure, certain parameters, including maximum lattice temperature, are improved by introducing certain process changes to provide for SCR-like characteristics during ESD events. A p+region is formed adjacent the collector to define a SCR-like emitter and with a common contact with the collector of the BJT. The p+ region is spaced from the n-emitter of the transistor by a n-epitaxial region, and the collector is preferably spaced further from the n-emitter than is the case in a regular BJT.

Abstract: In a system and method to reduce wafer breakages in a wafer handling system, the position of a wafer on a platen is monitored and closing of the platen on a vacuum chamber is prevented if a misaligned wafer is detected. In one embodiment the wafer position is monitored by monitoring the air pressure in vacuum channels of a platen faceplate.

Abstract: In an ESD protection device making use of a LVTSCR, at least one contacted drain and at least one emitter are formed, and are arranged laterally next to each other to be substantially equidistant from the gate of the LVTSCR, to improve holding voltage and decrease size. The ratio of emitter width to contacted drain width is adjusted to achieve the desired characteristics.

Abstract: In an ESD protection circuit, diodes for shunting current through an ESD clamp include a third terminal in order to provide a dual current path through the diode structure and provide for a voltage drop to the input of the protected internal circuit. In another embodiment, where a bipolar junction transistor is used as an ESD clamp to shunt current to ground between an I/O pad and an input to a protected internal circuit, a lower voltage is provided to the internal circuit by providing a voltage drop across an internal resistive element of the bipolar junction transistor. This is achieved by making use of two base terminals, one connected to the I/O pad, and the other connected to the input of the internal circuit and spaced from the first contact by the base polysilicon region of the bipolar junction transistor.

Abstract: In a circuit and method for adjusting rise-and-fall-time changes in an output driver signal due to changes in temperature, process or voltage, the driver output voltage is monitored and current flow through a constant load resistor adjusted as the voltage changes. The current may be adjusted by controlling the gate-source voltage on a transistor. The gate voltage on the transistor may also be used to adjust the power supply to pre-drivers of the output driver.

Abstract: In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming contacts or plugs in thick oxide holes that span across the regions to be interconnected.

Abstract: In a BJT ESD protection structure, the ESD current density is stabilized by partially blocking one or more of the emitter and n+ collector, sinker, and n-buried layer to define a comb-like structure for the partially blocked regions.

Abstract: In a BSCR and method of making a BSCR, a npn BJT structure is created and a p+ region is provided that is connected to the collector of the BJT, and one or more of the NBL, sinker and n+ collector of the BJT are partially blocked. In this way the NBL is formed into a comb-like NBL with a plurality of tines in one embodiment. The sinker and n+ collector may also be formed into a plurality islands. Furthermore, the period of the tines and islands may be varied to provide the desired BSCR characteristics.

Abstract: In a MOS array, current loss at distances further away from the drain and source contacts is compensated for by adjusting the length of the polygate. In an array with drain and source contacts near the middle of the structure, the length of the polygate tapers off along the width of the polygate towards both ends of the polygate.

Abstract: In an ESD protection device using a LVTSCR-like structure, the holding voltage is increased by placing the p+ emitter outside the drain of the device, thereby retarding the injection of holes from the p+ emitter. The p+ emitter may be implemented in one or more emitter regions formed outside the drain. The drain is split between a n+ drain and a floating n+ region near the gate to avoid excessive avalanche injection and resultant local overheating.

Abstract: In a high tolerance I/O interface with over-voltage protection during 5V tolerant mode and back-drive mode, includes pass gate circuitry to isolate the output of the driver circuit and input of the receiver circuit from the pad voltage during stress mode. The gate voltage of the PMOS transistor of the pass gate is charged up to avoid gate oxide breakdown during stress mode. Also, the gate and well of the driver pull-up transistor are charged to NG1 to avoid current flow through the transistor and to its well.

Abstract: A method for non-destructively testing an IC device to determine the ESD performance. A laser beam is used to probe the diffusions of the device. The amount of light absorbed by the diffusions is determined by monitoring the degree to which light is reflected by the device. The amount of reflection is related to the ESD susceptibility of the device in that the greater the amount of reflection, the worse the ESD performance of the device.

Abstract: In a Bi-CMOS ESD protection device, dual voltage capabilities are achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. The device may be asymmetrical to accommodate different voltage amplitudes in the positive and negative directions.

Abstract: In a differential global positioning system that includes one or more base stations and rover units, a system and method for including a radio modem transceiver in the rover units, and packaging several components, including the transceiver and a radio antenna in a single package, and possibly including re-chargeable batteries, a GPS receiver, and a GPS antenna in the package, to reduce the number of external electrical connections. Several of the components may be packaged into a survey range pole. GPS satellite correction information is transmitted from a base station in response to a request transmitted from the rover unit by means of the radio modem transceiver. Automatic channel selection is performed by the base stations to select a channel having low communication traffic. The rover units scan the available channels for valid GPS correction information and, in the event that more than one such channel is located, select the channel with the strongest signal.

Abstract: In a LDMOS transistor or matrix of transistors, hot carrier degradation effects are reduced by providing a ring drain and providing the ring drain with an overvoltage bias relative to the internal drain(s) of the LDMOS transistors.

Abstract: In an ESD protection device using a LVTSCR-like structure, the holding voltage is increased by placing the p+ emitter outside the drain of the device, thereby retarding the injection of holes from the p+ emitter. The p+ emitter may be implemented in one or more emitter regions formed outside the drain. The drain is split between a n+ drain and a floating n+ region near the gate to avoid excessive avalanche injection and resultant local overheating.

Abstract: In a Bi-CM0S ESD protection structure, the holding voltage is increased by a desired amount by including a NBL of chosen length. The positioning of the NBL may be adjusted to adjust the I-V characteristics of the structure. Dual voltage capabilities may be achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. Over and above the NBL position being adjusted relative to the p-regions, the two p-regions may vary in doping level, and dimensions to achieve different I-V characteristics for the device in the positive and negative directions.

Abstract: A method and system for packaging draperies includes the use of a packaging element. The packaging element has a central core having a C-shaped configuration which is sandwiched between two side panels. A drapery is wound around the core to define a drapery package which is packed into a carton with other drapery packages for shipping.

Abstract: In a one-shot, the pulse duration is adjustable through the use of a counter and one or more programmable delay lines in one or more of the feedback loops of the one-shot. The one-shot makes use of at least two flip-flops, and the output of the counter resets the flip-flops.

Abstract: In a non-overlap clock generator circuit providing two-phase clock signals, the clock-to-Q delay of memory elements is used to define the non-overlap times. The non-overlap time can be programmed in increments of the clock-to-Q delay of a standard memory element.