Patents Represented by Attorney Justin Oppenheimer Wolff & Donnelly LLP Boyce
  • Patent number: 6167319
    Abstract: A process is provided for generating a flow chart representing a control program defined by associative relationships between program levels, states and conditions, each condition specifying a transition from an associated one of the states as a source state to a corresponding selected destination state upon satisfaction of the condition during execution of the control program by the logic control unit. Each program level defines a sub-process of the control program.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: December 26, 2000
    Assignee: Scientronix, Inc.
    Inventors: Richard Harris, Jack Wiens
  • Patent number: 6149522
    Abstract: Authentication of a casino game data set is carried out within the casino game console using an authentication program stored in an unalterable ROM physically located within the casino game console. The casino game data set and a unique signature are stored in a mass storage device, which may comprise a read only unit or a read/write unit and which may be physically located either within the casino game console or remotely located and linked to the casino game console over a suitable network. The authentication program stored in the unalterable ROM performs an authentication check on the casino game data set at appropriate times, such as prior to commencement of game play, at periodic intervals or upon demand.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: November 21, 2000
    Assignee: Silicon Gaming - Nevada
    Inventors: Allan E. Alcorn, Michael Barnett, Louis D Giacalone, Jr., Adam E. Levinthal
  • Patent number: 6005807
    Abstract: A method for fabricating a split gate memory cell using the self-alignment technique to reduce the amount of misalignment is disclosed. The memory cell generally comprises a floating gate for storing a charge, a select gate for selecting one or more memory cell to operate thereon, a control gate, a buried source region and a buried drain region. Due to the structure of the memory cell, there is no read disturbance when reading the memory cell and its low voltage requirement makes it suitable for low voltage applications. When placed in a memory array, each of the memory cells in the array can be individually programmed or read. In performing the erase operation, a column of information is erased.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: December 21, 1999
    Assignee: Winbond Electronics Corp.
    Inventor: Bin-Shing Chen