Abstract: The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the storage pipeline experiences a cache miss and the instruction unit decides to switch threads, the instruction unit begins processing a second thread. The instruction unit also issues a data request to the storage control unit to obtain the missing data. During processing of the second thread, unused slots will appear in the storage pipeline because it is not possible to always dispatch instructions to completely keep the pipelines filled.

Abstract: A very long instruction word (VLIW) architecture and method provide for functionally expanding a parcel. The instruction register of the VLIW architecture is divided into a plurality of parcels, each of which has corresponding processing logic. The processing logic performs various functions based on the data within the corresponding parcel. A single parcel, however, can only specify a limited number of functions or include a limited amount of data for processing such that the level of optimization for a given VLIW may be impeded. The selector logic and processing logic, however, allow for data from a non-corresponding parcel to be selected and processed. In this manner, the functions and/or amount of data for processing in a single parcel can be expanded by using data from a non-corresponding parcel.