Abstract: A graphical user interface for a videophone in a cable television system allows the user to access the videophone functionalities with an input control device and a television monitor. The user can place a call, receive a call and store/access/call addresses using a remote in conjunction with the graphical user interface display screens. The videophone has several elements including a user interface, a graphics engine, a network interface, a remote control interface, and an output audio/video line connected to a television monitor. The user interface receives and processes control inputs using a microprocessor and the graphics engine generates the display screens using a DSP. Depending on processing requirements, the DSP may implement the user interface rather than the microprocessor. Also, anti-aliasing fonts are used to generate a high quality display. To save processing cycles, the anti-aliasing fonts may be retrieved from a look-up table rather than being generated in real time.

Abstract: A protection circuit prevents a surge applied to one end of a signal line from being applied to a circuit connected to another end of the signal line. The protection circuit includes a first diode having an anode coupled to the signal line and a first capacitor having a first electrode coupled to a cathode of the first diode and a second electrode coupled to a first potential. A second capacitor has a first electrode coupled to the signal line and a second diode has a cathode coupled to a second electrode of said second capacitor and an anode coupled to the first potential. A first inductor is coupled between the cathode of the first diode and the cathode of the second diode. A power supply terminal is applied with a power supply potential and is coupled to one end of the first inductor.

Abstract: A charge coupled device (CCD) camera includes a CCD imager circuit, a compression engine, and a control circuit coupled to both the CCD imager circuit and the compression engine. The CCD imager circuit is characterized by an integration time defined by clock pulses from the control circuit. The compression engine generates successive frame requests. The control circuit generates the clock pulses to define the integration time based on a time between the sucessive frame requests. The camera further includes a histogram accumulator and an automatic gain controlled (AGC) amplifier coupled between the CCD imager circuit and the histogram accumulator. The CCD imager circuit is characterized by a predetermined maximum imager dynamic range and generates successive frames of imager data values, each successive frame of imager data values being characterized by an imager data value dynamic range and each frame of imager data values being generated based on a corresponding integration time.

Abstract: In a two way cable system that includes a controller and a plurality of user terminals, a method of granting rights for upstream data transmission from the user terminals includes processing contention requests to generate contention grants and maintaining a list of connections, each connection having specified therefor a predetermined bit rate. The controller sends a downstream data stream to the user terminals and receives an upstream data stream from the user terminals. The downstream data stream includes a plurality of grant fields, and the upstream data stream includes upstream data slots and upstream control slots.

Abstract: A distortion circuit for linearizing third-, fifth- and seventh-order distortion components in a non-linear optical communications system includes at least one group of series connected diodes coupled to a common input terminal for receiving a signal source at one end and to an inductor and a capacitor at the other end, a resistance coupled to the common input terminal and a bias source for providing a bias current to the group of series connected diodes. The distortion circuit may be implemented as a predistortion circuit in the headend of the optical communications system or as a postdistortion circuit at the receiving end.

Abstract: A block phase estimator include a phase averaging circuit. A first embodiment of the phase averaging circuit includes a phase differencing circuit coupled to an averager input, a first modulo circuit coupled to the phase differencing circuit, a filter coupled to the first modulo circuit, and a summation circuit having an positive input and a negative input, the positive input being coupled to the averager input, the negative input being coupled to the filter. The phase averaging circuit further includes a second modulo circuit coupled to the summation circuit. An alternative embodiment of the phase averaging circuit includes a delay line having a plurality of taps coupled to an averager input and a plurality of first subtractor circuits, a first input of each first subtractor circuit being coupled to the averager input, a second input of each first subtractor circuit being coupled to a corresponding tap of the plurality of taps.

Abstract: A system for downloading different versions of software or data modules into a plurality of terminals having different compatibility interfaces includes an authoring component for generating the different module versions, a downloading source including a descriptor table which associates each module version with a list of compatibility requirements needed to download the module, and a plurality of terminals coupled to the downloading source. The downloading source transmits the descriptor table to each terminal and also continuously transmits the modules over the network. Each terminal extracts the descriptor table and, based on a match between an entry in the descriptor table and an internally stored table determines which version of a particular module should be downloaded. The system avoids the need for two-way communication between each terminal and the downloading source.

Abstract: A communication system for communicating low latency data in a fading channel environment using a data structure having data frames modulated on a subcarrier signal and on a commercial radio channel bandwidth. Low latency data is updated relatively rapidly at the low latency data generator. Because of this constant changing of low latency data at the point of generation in the transmitter end, the present invention communicates low latency data from the transmitter end to the receiver end of the communication system with relatively low delay. This communication system encodes and decodes low latency data using a single block encoding/decoding scheme. Such an encoding/decoding scheme introduces relatively less delay during the encoding/decoding processes while ensuring satisfactory data integrity for data communication in a fading channel environment.

Abstract: An encryption control system to process an input transport data stream into an output transport data stream includes an input demultiplexer, a first secure microprocessor, a second secure microprocessor and an output multiplexer. The input transport data stream includes first entitlement managment message data. The input demultiplexer culls the first entitlement managment message data from the input transport data stream, the first entitlement management message data including an encrypted multi-session key. The first secure microprocessor processes the first entitlement management message data to recover the multi-session key by decrypting the encrypted multi-session key using a first algorithm. The second secure microprocessor re-encrypts the multi-session key using a second algorithm and formats second entitlement management message data based on the first entitlement management message data with the re-encrypted multi-session key substituted for the encrypted multi-session key.

Abstract: A method for upgrading a computer operating system of a computer system, for example, a communications receiver includes a main processor, a slave processor, a first memory, and a second memory, wherein an existing operating system resides in the first memory. The first memory is attached to the main processor and the second memory is attached to the slave processor. The method comprises the steps of receiving a new operating system in the second memory; erasing the existing operating system from the first memory; and loading the new operating system into the first memory. In a communications receiver such as a satellite business receiver for receiving and decoding video, audio and data bitstreams, the first memory may be FLASH memory and the second memory may be cache memory of a video processor, and, more particularly, a video random access memory.

Abstract: A housing for heat emitting components includes a housing body and a housing cover. The housing cover includes an interior portion occupied by the heat emitting components when the housing body engages the housing cover, and a volumetric cooling element including a plurality of internal fins arranged to occupy a volume adjacent to the interior portion of the housing cover when the housing body engages the housing cover, wherein the internal fins volumetrically cool the volume.

Abstract: An optical modulator for a high power laser transmitter includes a laser source coupled through a phase modulator to a signal modulator. A noise source provides a band limited noise signal to either the laser source or the phase modulator or both. Alternatively, an optical modulator for a high power laser transmitter includes a laser source providing a laser output optical signal and a phase modulator. First and second continuous wave signals at respective first and second frequencies are combined to modulate either the laser source or the phase modulator. The first frequency is different than the second frequency. The laser and phase modulation produces a broadened optical output signal such that the broadened optical output signal is characterized by beat frequencies harmonically related to the first and second frequencies. The modulation bandwidth includes no significant beat frequencies.

Abstract: A heat sink assembly includes a printed wiring board, a metal case and a circuit package containing a gallium arsenide field effect transistor heat dissipating circuit. The circuit package includes a metal slug formed integrally with the circuit package, the heat dissipating circuit being bonded to an obverse surface of the metal slug. The printed wiring board includes first and second metal lands, the first metal land being disposed on an obverse surface of the printed wiring board, the second metal land being disposed on a reverse surface of the printed wiring board. A solder film is formed bonded to and thermally coupling a reverse surface of the metal slug to the first metal land, and a plurality of solder posts are formed, each post bonding to and thermally coupling the first metal land to the second metal land. The metal case is pressed against the second metal land with a grease film of thermally conductive grease squeezed therebetween.

Abstract: A communication system for coupling telephony or other signals to a broadband network such as a CATV network. The system transmits a multiplex of telephony signals in the forward band of the broadband network, with individual signals directed to an addressed subscriber. Telephony signals returning from subscribers upstream to a headend unit (HIU) are modulated onto the reverse band of the broadband network in a frequency division multiple access (FDMA) arrangement. The upstream modulated telephony signals are received at a telephony network interface at the HIU coupled to the broadband network. A group of reverse band modulated telephony signals are received at a group receiver or channelizer. The group receiver processes all upstream telephony signals within a selected spectral subband in the reverse band to apply a receiver matched filter with a weighted overlap and add circuit, and are then converted to baseband by an FFT circuit.

Abstract: In a communications system, a headend is provided with redundancy circuitry for video receivers, decoders, and modulation circuitry. The devices in the headend are monitored for failure, and when they fail, the channel being processed by the failing device is rerouted through redundancy circuitry to avoid the interruption of service to subscribers.

Abstract: A flexible architecture for a digital data receiver including a demultiplexer is provided which allows modular addition of data processors with low complexity and minimal memory requirements. The demultiplexer operates on a scalable frame-based multiplex signal, and interprets the multiplex control data at the start of the frame. With the information interpreted from the control data, the demultiplexer separates individual data services and optionally decrypts them. Data, a data clock and an error flag signal are presented to the demultiplexer input. According to a service requested by a user, the demultiplexer outputs decrypted data clock, error flag and service enable signals in a flow-through manner to an appropriate data processor without data storage.

Abstract: A combined IRD scrambler/modulator is provided in a headend. A service provider transmits a digital program signal in a digital data stream to a headend which distributes analog program signal to at least one subscriber. The headend receives an encoded digital program signal in the digital data stream from the service provider and decrypts the digital program signal therefrom. The digital program signal includes an audio and a video portion. The video portion of the signal is scrambled by a scrambler. The digital audio portion of the digital program signal and scrambled video portion of the digital program signal are converted to an analog program signal and transmitted to one or more subscribers.

Abstract: The present invention provides a tap off unit for use in a multiple dwelling unit. The tap off unit includes a housing having an input terminal and an output terminal for interposing the tap off unit in a cable signal line, a plurality of taps disposed within the housing, with each tap having a faceplate including associated signal coupling circuitry, and a circuitry board disposed within the housing. The circuitry board distributes a signal from the cable signal line to each of the plurality of taps within the housing and the plurality of taps are connected in parallel such that one of the plurality of taps may be removed without disruption of the signal to the remaining taps.

Abstract: A regulated power supply for application in a cable signal distribution amplifier comprises a filter, voltage doubler and current sense transformer controlled by a control technique known in the art. In the event of a high impedance short condition causing severe overcurrents, the known control technique is ineffective. To alleviate the problem, a high impedance current fault control circuit includes a sampling circuit, a level adjusting circuit, a differential amplifier for providing a monitor output control voltage and a buffer circuit to the controller. In the event of a high impedance current fault, the control circuit kicks in and interrupts controller operation saving power supply components from damage caused by the overcurrent condition.