Abstract: Within a content addressable memory, the latency in a memory access is reduced by combining the steps of effective address generation addition and searching within the content-addressable memory. Two inputs to the content-addressable memory are conditioned and then supplied to matching cells, which determine which address stored in the content-addressable memory will be output. This is accomplished without a full adder being implemented to add the two input operands before being supplied to the content-addressable memory.

Abstract: A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.

Abstract: A multitude of devices coupled to a processor are each given a location code, which is then displayed in proximity to each of the devices. Then, when the processor indicates an error within a particular device, the service person can easily find which device has the error by the displayed location code associated with the device.

Abstract: A register file array for storing or outputting binary logic bits of information encoded in 2B format is disclosed. The array includes an integrated 2B encoder which encodes stored information in 2B format before access by a read port to provide 2B formatted output without significantly affecting memory access time.

Abstract: The present invention addresses the foregoing need by providing a memory sensing circuit for accelerating a logic level transition of the complementary memory bit line of a complementary bit line pair having a full logic swing. The memory sensing circuit has a dual-rail circuit and at least one slew-rate acceleration circuit. The dual-rail circuit can be coupled across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines. The at least one slew-rate acceleration circuit is coupled to the dual-rail circuit. The conditioned signal is input to the slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive the conditioned signal. A feed-back loop transistor, having a gate terminal coupled to an output terminal of the inverter circuit is responsive to an output signal placed on the output terminal such that the slew-rate of the conditioned signal is accelerated.

Abstract: In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit. The store instruction is completed when all older instructions have completed and when all instructions in the instruction group have finished.

Abstract: A field emission cathode for use in flat panel displays is disclosed comprising a layer of conductive material and a layer of amorphic diamond film, functioning as a low effective work-function material, deposited over the conductive material to form emission sites. The emission sites each contain at least two sub-regions having differing electron affinities. Use of the cathode to form a computer screen is also disclosed along with the use of the cathode to form a fluorescent light source.

Abstract: A field emission lamp, of either a diode or triode structure has a packaging whereby electrical access to the various electrodes of the lamp is provided through the rear or underside of the field emission device so that the individual lamps can be placed in close proximity to each other.

Abstract: An edge triggered latch has an improved transparency window, which is essentially the delay of the N-stack pull-down tree. This minimizes the delay yet guarantees that the circuit will have enough time to evaluate the input data, since the evaluation is limited by the pulse width. This circuit eliminates early mode failure for latches placed in series, without the requirement of delay padding.

Abstract: On a field emission cathode, emission from the edges of metal conducting feedlines is inhibited, or even eliminated, by depositing a dielectric film over the edges before deposition of the field emitter material. Surface treatment of the metal conducting feedlines or substrate may be performed to enhance the field emission properties of the field emitter at preferential locations.

Abstract: In order to transmit several data words in succession over a bus between components in a data processing system, the skew between the various bus lines has to be compensated in order that each data word is accurately received. The skew compensation is implemented by setting predetermined delays on certain bus lines in response to the comparison of a test pattern with an ideal situation.

Abstract: A wafer polishing machine uses a pedestal unit that holds a semiconductor wafer using a vacuum force for polishing the surface of the wafer on a polishing pad and slurry mixture. A gimbal mechanism is implemented within the pedestal unit so that the various portions of the wafer surface are evenly polished. The gimbal mechanism enables the portion of the pedestal unit holding the semiconductor wafer to precess relative to that portion of the pedestal unit connected to the polishing machine. An elastomeric shim ring is also used within the pedestal unit to provide further compliance of the wafer surface to the various contours of the polishing pad during the polishing process.

Abstract: Performance is increased within a dynamic multiplexer by removing the foot device and replacing it with a logic gate (such as an OR, NOR, or NAND gate) receiving the select signals and activating the precharge device within the dynamic multiplexer circuit. With such a configuration, crowbar current is still inhibited.

Abstract: A cathode assembly includes a substrate (1101), a plurality of electrically conductive strips (1102), nano-size diamond particles (1701), and a layer (1801) of diamond material deposited (CVD) over the diamond particles (1701).

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A driver circuit has an output node coupled to a chip pad. A first PFET and a first resistor are connected between a power supply and the output node, wherein the first resistor is connected between the first PFET and the output node. A first NFET and a second resistor are connected between a ground potential and the output node, wherein the second resistor is connected between the first NFET and the output node. A third resistor is connected between an input to the driver circuit and a gate electrode of the first PFET. A fourth resistor is connected between the input to the driver circuit and a gate electrode of the first NFET. The pre-drive circuitry for driving the input to the PFET may include an NFET coupled between the ground potential and the input, wherein the gate electrode of the NFET receives the data signal to be driven.

Abstract: Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.

Abstract: A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.

Abstract: A data processing system includes logic to ensure result data stored in a history buffer is in a correct chronological order and is not overwritten until an appropriate point in time. The logic also ensures that the history buffer is able to capture result data that is produced with unexpected delays. The history buffer entries act as a "backup" for an architected register by storing older result data and rely on unique target identifiers assigned to dispatched instructions to keep the result data in a correct chronological order. Furthermore, a target identifier field of the architected register holds the latest target identifier assigned to a youngest instruction that modifies the architected register. Additionally, previous result data in the register is backed up in an allocated history buffer entry. If the result data is not yet available, the target identifier in the register will be deposited in the target identifier field of the history buffer entry.

Abstract: A telephone and voice mail (voice processing) system, which is implemented using only a single processing system for controlling operation of both the telephone system and the voice mail system, permits a user to call back a party using caller ID data stored with a voice mail message left by the party calling into the system. This is accomplished by storing caller ID information associated with an incoming call along with the message placed by the incoming caller and stored within the mailbox associated with the called party. Additionally, the caller ID information may be used to create a speed dial list within the telephone and voice mail system for later use by the user. Such caller ID information may be retrieved from a voice mail message left by the calling party, or may be retrieved while conducting a conversation with the incoming call.