Abstract: An antifuse structure according to a first aspect of the present invention is programmed by snap-back breakdown and includes a semiconductor substrate of a first conductivity type, an insulating layer over the surface of the semiconductor substrate, a conductive gate disposed over the insulating layer, spacer elements disposed at the outer edges of the conductive gate, spaced-apart first and second lightly doped regions of a second conductivity type disposed in the semiconductor substrate, the first and second lightly doped regions aligned to the edges of the conductive gate, third and fourth more heavily doped regions of the second conductivity type disposed in the semiconductor substrate, the third and fourth regions contiguous with the first and second regions, respectively, and aligned to the edges of the spacer elements, and a conductive filament in the insulating layer connecting the conductive gate to one of the second and fourth doped regions.

Abstract: An adaptable current mirror includes first and second MOS transistors. The first MOS transistor has its gate connected to its drain. A MOS capacitor structure is connected in series between the gate of the first MOS transistor and the gate of the second MOS transistor. Electrons may be placed onto and removed in an analog manner from a floating node associated with the second MOS transistor, usually the gate of the transistor, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. A plurality of adaptable current mirrors communicating with a plurality of current-carrying lines may be employed for indicating the output of the one of the plurality of current-carrying lines through which the most current is flowing.

Abstract: An adaptable MOS winner take all circuit includes a plurality of adaptable current mirrors. Each adaptable current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures. Electrons may be placed onto and removed from a floating node associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.

Abstract: Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance anti-fuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath.

Abstract: A mechanism is provided for maintaining an open door in a selected fixed position includes a keyed shaft which passes through a plurality of elliptically shaped discs via apertures centrally located in the discs are mounted. The long axis of each disc is aligned to that of the other discs and the discs are pressed together from either side along the axis of the shaft between two compression springs. Angled stop members located to the outside of the compression springs displace the discs along their long axis at a small angle from the plane perpendicular to the shaft. The small angle is chosen to produce a substantially circular projection of the discs in a plane perpendicular to the shaft. The shaft, with its mounted discs, springs, and angled stop members, is placed within a housing of cylindrical cross section having an interior diameter selected such that the discs are in frictional contact with the internal surface of the housing and the shaft is thus slidably but frictionally disposed in the housing.

Abstract: A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications.

Abstract: A process is provided for making a semiconductor element comprising a single-crystal layer of silicon on a diamond insulator.

Abstract: The present invention includes four approaches to reduce the unintended programming of antifuses while programming selected antifuses and to decrease the programming time. The first approach includes circuitry to maintain the voltage placed on unselected antifuses at a constant level by use of a voltage source. According to the second approach, a resistor is included in series with the voltage source. According to the third approach, a diode is included in series with the voltage source. According to the fourth approach, a MOS implementation of a diode is included in series with the voltage source.

Abstract: A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.

Abstract: A small diameter multimode optical fiber with a low numerical aperture (i.e., 0.1) is used as a microlens to collimate the output emissions of a laser diode before butt coupling the output of the laser diode to an optical fiber. The optical fiber used as the microlens is chosen such that its diameter roughly equals the diameter of the fiber to be coupled to the laser diode. The collimation is performed in the high NA direction of the output of the laser diode. The output of a bundle of butt coupled optical fibers may be used to pump a laser system.

Abstract: An already- programmed anti-fuse is DC soaked by passing DC current through the anti-fuse from a DC voltage source applied across the electrodes of the anti-fuse. The anti-fuse resistance is lower when the DC voltage being applied such that the positive end of the voltage source is applied to the electrode having the higher arsenic concentration.An already programmed anti-fuse is AC soaked, by passing alternating current pulses through the anti-fuse from an AC voltage source applied across the anti-fuse electrodes. This AC soak may even be applied following the controlled polarity DC soak disclosed herein. The AC soaked anti-fuse resistance is even lower than DC soaked anti-fuse under the same soak current level.

Abstract: An MOS current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures in order to adapt the current mirror to supply a desired output current when a particular input calibration current is present.

Abstract: A connector arrangement for connecting together a plurality of circuit boards includes a plurality of side insertion connectors of a first mating type are mounted parallel to one another on parallel finger portions extending from body portions of one or more first circuit boards. A plurality of side insertion type connectors of a second mating type are mounted on a plurality of second circuit boards. The side insertion type connectors of the second type are mounted at positions and orientations on the second circuit boards chosen such that they are engageable with the mating connectors of the first type mounted on the first circuit boards. When connected by the mating connectors, the first and second circuit boards will be disposed at right angles to one another.

Abstract: A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remians in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalanching a junction associated with it. In a preferred embodiment, a buried contact if formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor.

Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Abstract: An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.

Abstract: A user-programmable integrated circuit includes an analog portion containing user-configurable analog circuit modules, a digital portion containing user-configurable digital circuit modules, an interface portion containing user-configurable interface circuits for conversion of signals from analog to digital form and from digital to analog form, and a user-configurable interconnection and input/output architecture.

Abstract: A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.

Abstract: A CMOS single phase register includes two pairs of cross coupled CMOS inverters connected together by transistor switches. The first pair of cross-coupled CMOS inverters is connected to a complementary pair of data inputs through a first pair of transistor switches which turn on in response to a first logic level. The complementary outputs of the first pair of cross-coupled CMOS inverters is connected to the inputs of the second pair of cross-coupled CMOS inverters through a second pair of transistor switches which turn on in response to a second logic level. The complementary outputs of the CMOS single phase register of the present invention are the outputs of the second pair of cross-coupled CMOS inverters. The ground connections of the first pair of cross-coupled CMOS inverters is made through a transistor switch which turns on in response to the first logic level.

Abstract: A MIDI-compatible musical instrument controller includes a keyboard having a plurality of keys and circuitry for electronically scanning the keyboard and for producing individual key-depression signals for each key being depressed. Each of the individual key depression signals identifies the key with which it is associated, commences when the key is depressed, and terminates when the key with which it is associated is released. A plurality of note tables is provided for converting each of the individual key depression signals to MIDI note-identifying information. Each note table defines each key as one or more preselected musical notes such that no two of such tables define the plurality of keys with the same MIDI note-identifying information. One of the note tables is selected in response to a user command.