Abstract: A structure for protecting chemical mechanical polishing (CMP) apparatus components from corrosion includes a refractory metal oxide coating layer (33) formed over surfaces of a platen (32). In a preferred embodiment, the refractory metal oxide coating layer (33) is a plasma-flame sprayed chromium-oxide layer. In an alternative embodiment, a sealer layer (42) is placed at least within pores (41) of refractory metal oxide coating layer (33) for additional protection. The refractory metal oxide coating layer (33) is also suitable for protecting other CMP apparatus components that are susceptible to corrosion.

Abstract: An insulated gate field effect transistor (IGFET) structure (10) includes a source region (14) and a drain region (16) formed in an impurity well (13). A channel region (18) separates the source region (14) from the drain region (16). In one embodiment, a unilateral extension region (17) is formed adjacent the source region (14) only and extends into the channel region (18). The unilateral extension region (17) has a peak dopant concentration at a depth (23) and a lateral distance (24) to provide punchthrough resistance. The IGFET structure (10) is suitable for low (i.e., 0.2-0.3 volts) to medium (0.5-0.6 volts) threshold voltage reduced channel length applications.

Abstract: A semiconductor structure having an edge termination feature wherein a first doped region and a second doped region are selectively formed in a semiconductor layer. The second doped region is coupled with the first doped region and has an impurity concentration less than that of the first doped region. An insulating layer is disposed over the semiconductor layer and over at least a portion of the second doped region. A conductive layer, having a coil-shaped configuration, is disposed over the insulating layer and is coupled to the semiconductor layer.

Abstract: A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.

Abstract: A vertical IGFET configuration includes a stripe arrangement having a non-linear shape. In one example, a stripe arrangement (30) has contact cut-out portions (41) and elongated portions (42). The elongated portions (42) have a width (44) that less than the width (43) of the contact cut-out portions (41). The stripe arrangement (30) increases channel density compared to typical individual cell configurations (10) and straight stripe configurations (20) thereby lowering on-resistance.

Abstract: A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Abstract: An enhanced mobility MOSFET device (10) comprises a channel layer (12) formed on a monocrystalline silicon layer (11). The channel layer (12) comprises an alloy of silicon and a second material with the second material substitutionally present in silicon lattice sites at an atomic percentage that places the channel layer (12) under a tensile stress.

Abstract: A process for using removable Z-axis anisotropically conductive adhesive material (21) which includes water, a matrix resin (23), and conductive spheres (22). The material (21) is suitable for providing temporary contact between electronic devices. In one embodiment, the material (21) is used to temporarily bond a semiconductor wafer (11) to a probe substrate (12) for wafer-level burn-in.

Abstract: A molded slotted optical switch structure (21) includes a separate molded emitter portion (23) and a separate molded detector portion (24). The molded emitter portion (23) includes an emitter device (29) molded within an emitter housing (27). The molded detector portion includes a detector device (49) molded within a detector housing (47). The molded emitter portion (23) is coupled to the molded detector portion (24) to form a slot (57) with the emitter device (29) and the detector device (49) aligned with each other across the slot (57). Switching occurs when an opaque object passes through the slot (57) interrupting optical communication between the emitter device (29) and the detector device (49).

Abstract: An improved method for polishing a semiconductor substrate includes forming a protective layer (21) on one major surface (24) of a substrate (19) to form a protected side and polishing an unprotected surface (26) of the substrate (19) with a double sided polisher (11). During the polishing process, material from the unprotected side (26) is removed at a faster rate than material from the protected side. The method provides a single side polished substrate (19) with improved flatness characteristics. In an additional embodiment, polishing pads (13,23) having different surface contact characteristics are used to support process automation.

Abstract: A ball-grid array (BGA) semiconductor package (10,60,90) includes a substrate (31,61,91) attached to a support substrate (32,62,92). The substrate (31,61,91) has an opening (33) extending from an upper surface to a lower surface. An integrated circuit chip (18) is attached to the support substrate (32,62,92) within the opening (33). Bond pads (22) on the integrated circuit chip (18) are electrically connected to ball pads (42,73,106,108) on the lower surface of the substrate (31,61,91). Conductive solder balls (26) are attached to the ball pads (42,73,106,108). The support substrate (32,62,92) provides a low profile and functions as a standoff that limits the collapse of the conductive solder balls (26) when the BGA semiconductor package (10,60,90) is attached to an application board (46).

Abstract: A method for making stable arsenic doped semiconductor devices (11,53,56) using dry etching techniques includes forming a polycrystalline semiconductor layer (29) on a upper surface of a semiconductor substrate (12), and patterning the polycrystalline semiconductor layer (29) using a dry etch process such as a plasma etch process. The semiconductor substrate (12) is then exposed to an elevated temperature to substantially reduce any defects contiguous with the upper surface of semiconductor substrate (12) resulting from the dry etch process. Arsenic is then incorporated into the semiconductor substrate (12) to form N+ regions (44). Surface sensitive devices such as MOSFET devices (53,56) are then formed on or within the semiconductor substrate (12).

Abstract: A method for forming a semiconductor device includes forming insulated gate regions (122,222) on a substrate (26) using a first photo-masking step, forming a base region (47) through an opening (143) between the insulated gate regions (122,222), and forming a source region (152) within the base region (47). Next, a protective layer (61) is formed and selectively patterned using a second photo-masking step to form an opening (62) within the first opening (143) and an opening (63) above one of the insulated gate regions (122). Next, a portion (66) of the substrate (26) and a portion (67) of the insulated gate region (122) are removed. Ohmic contacts (74,76) are then formed and patterned using a third photo-masking step. Additionally, a termination structure (81) is described.

Abstract: A vertically integrated sensor structure (60) includes a base substrate (71) and a cap substrate (72) bonded to the base substrate (71). The base substrate (71) includes a transducer (78) for sensing an environmental condition. The cap substrate (72) includes electronic devices (92) formed on one surface to process output signals from the transducer (78). The sensor structure (60) provides an integrated structure that isolates sensitive components from harsh environments.

Abstract: A method for making a schottky diode structure (10) simultaneously with a polysilicon contact structure (31,33) to a transistor is provided. In a single process step, a polysilicon layer is patterned to expose a single crystal semiconductor region (22a) over one portion of a substrate, while leaving portions the polysilicon layer (31, 33, 29) intact over other portions of the substrate (22b). Multi-layer metal electrodes are deposited and patterned to form a rectifying schottky contact to the exposed single crystal region (22a), and to form an ohmic contact to the exposed polysilicon (31, 33, 29).

Abstract: A high pressure sensor structure (11, 111, 211) includes a housing (12, 112, 212) having an upper cavity portion (13, 113, 213) and a lower cavity portion (16, 116, 216). A diaphragm (18, 118, 218) separates the upper cavity portion (13, 113, 213) from the lower cavity portion (16, 116, 216). A semiconductor chip (26, 126, 226) is attached to the upper surface of the diaphragm (18, 118, 218) within the upper cavity portion (13, 113, 213). The diaphragm (18, 118, 218) has a thickness (21, 121, 221) and an exposed width (23, 123, 223) such that the semiconductor chip (26, 126, 226) generates a measurable output signal when the lower surface of the diaphragm (18, 118, 218) is exposed to a high pressure environment.

Abstract: A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.

Abstract: A method for doping a strained heterojunction semiconductor device includes heating a substrate (16) having a strained mono-crystalline semiconductor region (22) to a temperature above room temperature. While the substrate (16) is heated, dopants are ion implanted into the strained mono-crystalline semiconductor region (22) to minimize implant related damage. Thereafter the substrate (16) is heated under non-steady state conditions for a time sufficient to activate the implanted dopant and anneal implant related damage while minimizing relaxation of the strained heterojunction.

Abstract: An enhanced mobility MOSFET device (10) comprises a channel layer (12) formed on a monocrystalline silicon layer (11). The channel layer (12) comprises an alloy of silicon and a second material with the second material substitutionally present in silicon lattice sites at an atomic percentage that places the channel layer (12) under a tensile stress.

Abstract: A semiconductor leadframe structure (11,41) includes a die bond portion (12) and a plurality of leads (13) coupled to the die bond portion (12). The leadframe structure (11) comprises a metal (23) such as copper or a copper alloy. At least one lead (28,29) includes a bond post (31) that has a major surface (32) for forming a wire bond. The major surface (32) includes an exposed area (33) of leadframe metal (23) and a covered area (34) of another metal (24) deposited onto the leadframe metal (23).