Abstract: A downstream plasma reactor system is presented. The reactor system includes a reaction chamber. An inlet conduit is connected to the reaction chamber. A plasma tube is coupled to the inlet conduit. A sealing member is interposed between the plasma tube and the inlet conduit. A blocking member, preferably containing a fluorocarbon polymer, is also interposed between the plasma tube and the inlet conduit. The blocking member is positioned closer to the discharge opening of the plasma tube than the sealing member and is preferably capable of preventing a substantial quantity of plasma-generated reactive species from reaching the sealing member during operation of the reactor system.

Abstract: An integrated circuit fabrication process is provided for placing a diffusion barrier layer above the junctions of a transistor and counter dopant regions at the boundaries of the junctions to enhance the dopant level within the junctions. The diffusion barrier layer (e.g., a nitride layer) is strategically placed between the junctions and sidewall spacers which extend laterally from the opposed sidewall surfaces of a gate conductor. The diffusion barrier layer inhibits the dopants within the junctions from passing into the sidewall spacers. Dopant species opposite in type to those in the junctions are implanted into the counter dopant regions using a "large tilt angle" (LTA) implant methodology, wherein the angle of incidence of the injected dopant ions is at a non-perpendicular angle relative to the upper surface of the semiconductor substrate. In this manner, the counter dopant regions are placed both beneath the junctions and at the juncture between the junctions and the channel region of the transistor.

Abstract: A fabrication process and transistor are described in which a transistor having a diffusion barrier located in the bottom layer of a stacked (i.e., multi-layer) gate conductor is formed, thereby reducing the diffusion of dopants from the gate conductor to the underlying channel region. In a general embodiment, multiple gate conductor layers are formed and arranged in a vertical stack, and a diffusion barrier is introduced into one or more layers of the stack. In a preferred dual-layer embodiment, a first gate conductor layer (i.e., the bottom layer) having a first thickness is deposited upon a gate dielectric layer. An argon distribution is then introduced into the first gate conductor layer to form an argon diffusion barrier in the first gate conductor layer. A second gate conductor layer having a second thickness is then deposited upon the first gate conductor layer.

Abstract: A method is provided for forming a multi-level interconnect in which capacitive coupling between laterally adjacent conductors employed by an integrated circuit is reduced. According to an embodiment, a conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the conductor. Select portions of the conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the conductor. An interlevel dielectric is deposited to a level above the masking structure such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the conductor, and the interlevel dielectric is planarized to a level spaced above an upper surface of the masking structure.

Abstract: A comb filter is provided for achieving substantial attenuation of aliasing or imaging bans of a signal to be filtered. The comb filter can perform decimation or interpolation, depending upon its application. Integration can include an integration term with adjustable voltage accumulation at a particular sample point in time. The accumulation factor can be an integer or fractional number and is introduced at a sample count value L within each of M number of samples formed by the rate change switch within the comb filter. The amount of gain being introduced can possibly vary depending on the number of accumulation cycles programmed within configuration registers of the digital signal processor which carries out the comb filter functions. The programmable accumulator avoids having to implement a multiplication operation and the complexities associated therewith.

Abstract: An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. The insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.

Abstract: A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective buses and further includes a plurality of queues placed within address and data paths linking the various controllers. An interface controller coupled between a peripheral bus (excluding the CPU local bus) determines if an address forwarded from a peripheral device is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If that address (i.e., target address) is not the first address (i.e., initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. An offset between the target address and the modified address is denoted as a count value. The initial address aligns the reads to a cacheline boundary and stores in successive order the quad words of the cacheline in the queue of the bus interface unit.

Abstract: A method, system, and memory storage medium for reducing variation of interconnect resistance of integrated circuits are provided. Interconnects are formed by a damascene process in which trenches are formed in an interlevel dielectric. The dimensions of the trenches are then measured. The dimension measurement results and the resistivity of the interconnect material are used to calculate a target thickness of interconnect material within the trench that gives a predetermined interconnect resistance. Interconnect material is then deposited within the trenches and upon the interlevel dielectric. A chemical-mechanical polishing process, which is used to remove interconnect material external to the trench, is then adjusted to leave the target thickness of interconnect material such that the completed interconnects have the predetermined resistance. Optionally, the resistance of the interconnects on the completed integrated circuits may be measured and compared to the predetermined interconnect resistance.

Abstract: A semiconductor process in which a first silicide is formed on silicon upper surfaces upon which a second silicide is selectively deposited. A refractory metal is blanket deposited on a semiconductor substrate. The semiconductor substrate is then heated to a first temperature to react portions of the refractory metal above the exposed silicon surfaces to form a first phase of a first silicide. The unreacted portions of the refractory metal then remove, typically with a wet etch process. The semiconductor substrate is then heated to a second temperature to form a second phase of the first silicide. The second temperature is typically greater than the first, and the resistivity of the second phase is less than a resistivity of the first phase. Thereafter, a second metal silicide is selectively deposited on the first silicide, preferably through the use of a chemical vapor deposition process.

Abstract: A high-reliability damascene interconnect structure and a method for forming the same are provided. An interlevel dielectric is formed over a semiconductor topography, and trenches for interconnects and/or vias are formed in the interlevel dielectric. A trench liner may then be deposited, followed by deposition of a low-resistance metal such as copper. The low-resistance metal deposition is preferably stopped before the trenches are entirely filled. Portions of the metal and trench liner external to the trenches are subsequently removed, such that low-resistance metal interconnect portions are formed. A high-melting-point metal, such as tungsten, is deposited over upper surfaces of the interconnect portions and interlevel dielectric. Portions of the high-melting-point metal are removed to form interconnects having a low-resistance metal lower portion and a high-melting-point metal upper portion.

Abstract: A method, circuit and apparatus is provided for preserving and/or correcting product engineering information. Non-volatile storage devices reserved for receiving product engineering bits can either be contained in at least three separate storage locations spaced from each other across the integrated circuit or, alternatively, be contained in a single storage location area with error correction bits and/or words added to that location. In the first instance, redundant product engineering bits are written to each storage location. Product engineering bits read from a majority of those locations which have identical values are deemed valid. The addition of extra bits and/or words can be combined with the possibly defective product engineering bits to correct errors in those bits.

Abstract: An integrated circuit fabrication process is provided for forming a transistor in which the channel length is mandated by the width of a gate conductor formed upon a gate dielectric having a dielectric constant greater than about 3.8. The thickness of the gate dielectric may be made sufficiently large to serve as a mask during subsequent implantation of impurities into a substrate. The gate conductor and the gate dielectric are first patterned using lithography and an etch step. In one embodiment, a masking layer is then formed across a select portion of the gate conductor and an ensuing source region of the substrate. The uncovered portion of the gate conductor is etched to expose a region of the gate dielectric. A first implant of impurities is forwarded into regions of the substrate not covered by the masking layer to form an LDD area underneath the exposed region of the gate dielectric and a heavily doped drain region laterally adjacent the LDD area.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned.

Abstract: An apparatus and method are presented for identifying a semiconductor die within a group of semiconductor dice formed upon a surface of the same semiconductor wafer. During wafer fabrication, several parallel-resonant electronic structures are formed within each die area of the semiconductor wafer. The parallel-resonant structures are configured such that each semiconductor die responds differently to an alternating current (a.c.) electrical signal. During an identification operation, an a.c. electrical signal is coupled to the parallel-resonant structures of a selected semiconductor die. The unique response of the parallel-resonant structures of the selected semiconductor die to the a.c. electrical signal is used to determine the position of the selected semiconductor die relative to other semiconductor dice formed from the same semiconductor wafer. The apparatus includes a includes a variable frequency oscillator configured to produce an a.c. voltage Vout, a probe, and a resistor.

Abstract: Disclosed is a method and circuit for detecting overflow when multiplying operands. The disclosed method and circuit is configured to operate in parallel with a multiplier configured to multiply first and second n bit operands. In general, the multiplier circuit generates result operand which represents a multiplication of the first and second n bit operands. An overflow detection circuit is coupled to the multiplier circuit and configured to generate an overflow signal which indicates that the multiplication of the first and second n bit operands results in an overflow condition. The multiplier circuit comprises a compression circuit configured to generate the first and second 2n bit partial product operands as a function of the first and second n bit operands. An addition of the first and second 2n bit partial product operands produces the result operand.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

Abstract: An apparatus for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors.

Abstract: A wafer disk pad is presented having one or more wafer loading points to facilitate wafer loading and unloading using a vacuum wand. The wafer loading points comprise grooves in a base plate. Each groove begins at a frontside surface of the base plate, extends under a portion of an upper surface of the base plate reserved for wafer placement, and is dimensioned to receive a tip of a vacuum wand. In one embodiment, the base plate includes a pair of grooves. A first groove is located on a left side of the wafer disk pad, and is conveniently located and oriented for left-handed operators. A second groove is located on a right side of the wafer disk pad, and is conveniently located and oriented for right-handed operators facing the frontside surface. Each groove is preferably sloped to facilitate separation of the semiconductor wafer from the pad. The depth of each groove is greatest at the frontside surface and decreases with increasing lateral distance into the base plate from the frontside surface.

Abstract: An integrated circuit, apparatus and method is provided for programming manufacturing information and software program information upon non-volatile storage elements on the integrated circuit. The manufacturing information includes information as to a specific processing recipe or layout used to form hardware of the integrated circuit. The software information indicates a specific revision of software used to program the integrated circuit, or a programming tool used to input the software into the integrated circuit. Combination of software and hardware is therefore embodied in non-volatile storage elements as product engineering bits. The product engineering bits can be called upon and read by the manufacturer or by the customer outside normal operation of the integrated circuit. A comparison of the hardware and software revisions will indicate possible incompatibility.

Abstract: A transistor is provided having a pair of sidewall spacers, each preferably including an ultrathin silicon nitride layer, adjacent to opposed sidewall surfaces of a gate conductor on a semiconductor substrate. Each spacer preferably includes a layer of thermally grown silicon nitride, and may also include a silicon dioxide layer. In an embodiment, the spacer includes a first silicon nitride layer adjacent to the sidewall surface, a silicon dioxide layer adjacent to the first silicon nitride layer, and a second silicon nitride layer adjacent to the silicon dioxide layer. Impurity distributions within the substrate may be aligned with any of the layers within the spacer, such that a distribution may be aligned with a sidewall surface or displaced outward from a sidewall surface. Such a distribution may be displaced outward by the lateral width of the spacer or by less than the lateral width of the spacer (i.e. the width of one or more layers within the spacer).