Patents Represented by Attorney Kirk Iandiorio and Teska Teska
  • Patent number: 6158347
    Abstract: A detonator with a base portion including a header wall terminating in a support surface; an initiator on the support surface; an explosive charge spaced from the initiator; and a cap having an interior top surface and an enclosure wall extending downward from the interior top surface and surrounding the initiator and the explosive charge. The wall terminates in a rim secured at a location along the header wall corresponding to the thickness of the initiator, the spacing between the initiator and the explosive charge, and the thickness of the explosive charge thereby ensuring that the explosive charge is in communication with the interior top surface of the cap.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: December 12, 2000
    Assignee: EG&G Star City, Inc.
    Inventors: Barry T. Neyer, John T. Adams, Robert J. Tomasoski
  • Patent number: 6147531
    Abstract: A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: November 14, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Kevin J. McCall, Janos Kovacs
  • Patent number: 6144981
    Abstract: A programmable pulse slimmer system for a low pass ladder filter includes a filter input current source for providing to a low pass ladder filter the input signal to be filtered; and a high frequency boost current source for injecting into the low pass ladder filter forward of the first inductor device a high frequency load current which is a scaled inverse replica of the input signal to provide gain at the high frequency end of the low pass band of the low pass ladder filter.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: November 7, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Janos Kovacs, Kevin J. McCall
  • Patent number: 6137579
    Abstract: A planar alignment system and method for aligning a first planar surface parallel to a second planar surface including: attaching a target base having a first planar reflective surface so that the first planar reflective surface is parallel to the first planar surface, positioning a reflector having a second planar reflective surface so that the second planar reflective surface is parallel to the second planar surface, positioning a planar target parallel to one of the planar surfaces, transmitting a radiation beam, at an angle perpendicular to one of the planar surfaces, from a radiation transmitter releasably attached to that planar surface, toward the planar reflective surface of the other planar surface, and reflecting the transmitted radiation beam between the planar reflective surfaces so that the reflected radiation beam strikes the planar target, producing a calibration point whose displacement from the originally transmitted radiation beam is indicative of the positional alignment between the first p
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: October 24, 2000
    Inventor: Peter Reilley
  • Patent number: 6128998
    Abstract: A continuous intersecting braided composite preform including a first member with at least one ply of biased fibers and a second member also with at least one ply of biased fiber. The first member intersects with the second member and passes continuously through the second member such that the biased fibers of the first member are interstitially arranged with respect to the biased fibers of the second member at the intersection.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: October 10, 2000
    Assignee: Foster Miller, Inc.
    Inventors: Glenn Freitas, Thomas Campbell, Garry Kasten
  • Patent number: 5422588
    Abstract: A low distortion CMOS switch system includes a plurality of N-channel and a plurality of P-channel transistors with their drain and source terminals connected in parallel for receiving an input signal to be switched; and a control circuit for providing a different positive drive voltage to the gate of each of the N-channel transistors and a different negative drive voltage to the gate of each of the P-channel transistors to produce substantially constant "on" resistance, R.sub.ON, throughout the range of the switched signal conducted through the drain and source terminals, and for providing the same negative drive voltage to the gate of each of the N channel transistors and the same positive drive voltage to the gate of each of the P channel transistors to turn off the transistors.
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: June 6, 1995
    Assignee: Analog Devices Inc.
    Inventor: John Wynne
  • Patent number: 5422583
    Abstract: An improved back gate switched sample and hold circuit includes a sample and hold channel including a sample switch having a back gate and a storage element; a back gate circuit for controlling the back gate of the sample switch; and a first attenuator circuit for scaling the input signal from a low impedance source for delivery to the sample switch and a second attenuator circuit responsive to the input signal from the low impedance source to independently drive the back gate circuit and isolate any distortion of the input signal in the back gate circuit from affecting the input signal in said sample and hold channel.
    Type: Grant
    Filed: March 8, 1994
    Date of Patent: June 6, 1995
    Assignee: Analog Devices Inc.
    Inventors: John Blake, Anthony Gribben, Colin Price
  • Patent number: 5414390
    Abstract: A center frequency controlled phase locked loop system includes a primary phase locked loop having a first voltage controlled oscillator including a first voltage to current converter whose output current drives a first current controlled oscillator to produce the primary clock signal to be locked onto an input signal; a second phase locked loop having a second voltage controlled oscillator including a second voltage to current converter whose output current drives a second current controlled oscillator to produce the synthesized clock signal whose frequency is approximately that of the input signal or integral multiple thereof; and a current copier circuit for copying the output current from the second voltage to current converter and delivering it to the first current controlled oscillator to maintain the center frequency of the first voltage controlled oscillator at approximately the output frequency of the synthesized clock signal.
    Type: Grant
    Filed: September 12, 1994
    Date of Patent: May 9, 1995
    Assignee: Analog Devices, Inc.
    Inventors: Janos Kovacs, Ronald Kroesen
  • Patent number: D359497
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: June 20, 1995
    Assignee: Jaden Loaders PTY, LTD
    Inventor: Alister G. Rayner