Abstract: A phase combining method and apparatus for use in a diversity reception radiotelephone is described. The phase combining method and apparatus is a hybrid diversity technique which combines elements of maximal ratio combining (MRC) and level comparison selection diversity, which results in a simple and effective implementation of a diversity receiver with superior performance. The diversity receiver demodulates the received signals, extracts the phase, forming two phase signals. Then, the two phase signals are combined to form a third phase signal. One of the three phase signals is selected to be used for interpretation of a symbol in the Quadrature Phase Shift Keying (QPSK) constellation. The selection process is based on the received signal strength of the received signals.

Abstract: A radio transceiver (119) including a transmitter (111), a receiver (107), and a controller (113). The controller (113) creates a fixed period reference signal (201) and a second reference signal (203) which has a variable delay in time from the fixed period reference signal (201). In addition the controller (113) creates a plurality of control signals used to control parts of the transceiver (119) and which are time dependant upon the second reference signal 203). Therefore, the adjusting of the variable delay of the second signal subsequently adjusts the plurality of control signals.

Abstract: A power amplifier controller for detecting saturation of the power amplifier (203) and corrects the automatic output control voltage (231) to avoid any further saturation. A detector (211) detects the power of the radio frequency (RF) output signal (211) and generates a signal (229) correlated to the detected power. Comparator (217) compares changes in that signal (229) to changes in the voltage of the AOC signal (231). The comparator (217) generates a signal (233) correlated to saturation of the power amplifier (203) for a DSP (223). The DSP (223) checks the status of this signal (233). Upon detecting saturation, an algorithm contained within the DSP methodically reduces the voltage of the AOC signal (231) until there is a change in the power of the RF output signal (211).

Abstract: The method of synchronizing a sampling clock signal to a received data signal, the clock recovery circuit generates several clock signals at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry generates error signals representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit then adjusts or maintains the phase of the symbol clock to provide the optimal sampling phase.

Abstract: The present disclosure includes a discussion of a Subscriber Identification Module (SIM) chip card reader (201). In the preferred embodiment, the SIM chip card reader is integrated into and sealed to a radiotelephone. A battery (105) for the radiotelephone (103) retains the SIM chip card (401) in the SIM chip card reader (201) while the radiotelephone (103) is operating. The SIM chip card reader (201) also includes a ejector knob (405) for removing the SIM chip card (401) from the SIM chip card reader (201).

Abstract: The present disclosure includes a discussion of a decision-directed clock recovery system which includes circuitry to prevent false-locking and accelerate acquisition on a known symbol patterns. The clock recovery system has at least two control circuits. Each control circuit has an effective bandwidth and also generates a clock signal. The clock recovery system samples the received data signal using the two clock signals, forming a corresponding first and second sampled signal. The sampled signals are used to generate corresponding symbol decisions. The symbol decision signals are processed to detect a known symbol pattern in the received data signal. Upon detection of the known bit sequence, the characteristics of the clock recovery system are modified, namely, the effective bandwidth of the control circuits are modified.

Abstract: A clock recovery circuit employs a method of and apparatus for adjusting the phase of a recovered clock signal. The clock signal is recovered from a received input signal. The clock recovery circuit generates a sampling clock signal which is synchronous with the received signal. Additionally, the phase adjustment apparatus generates at least two error signals which indicate the quality of the received signal at different sampling phases. The smallest error signal is referred to as the minimum error value. Each error signal is compared to the minimum error value, creating a corresponding normalized error magnitude signal. Each normalized error magnitude signal is processed to determine the desired phase of the sampling clock signal. Dependent upon the processing of the normalized error magnitude signals, the phase of the sampling clock signal is either shifted or maintained until the next sampling point.