Abstract: A liquid cooled circuit module comprises an integrated circuit package; a cover having a rim which lies against the integrated circuit package, the cover being shaped to form a passage for the liquid between the integrated circuit package and the cover; a retaining mechanism, which is fastened directly to the integrated circuit package, and which includes a member that extends above the cover; and a spring, which is held in compression between the cover and the retaining mechanism member; the spring being adapted to press the rim against the integrated circuit package with at least a predetermined minimal force which prevents leaks and at the same time not exceed a stress limit in the spring.

Abstract: A module for packaging and electrically interconnecting integrated circuit chips comprises: a porous ceramic substrate which has a major surface that is pitted by a portion of the pores. Voltage planes and ground planes lie internal to the substrate, and metal filled via holes feed through the substrate. A second material fills the pores in the major surface to form a pit free surface. This second material is of a type which resists abrasion substantially less than the ceramic substrate. And metal lines are disposed over the pit free surface for interconnecting the metal filled via holes to the integrated circuits.

Abstract: A program scanner for a processor having multiple internal streams of instruction and data flow scans a sequence of incoming codes, and employs a plurality of rams to detect various types of syllables in that code. The contents of these rams are signals indicating the various types of codes possible with the output of the rams then being multiplexed to provide an output indicating which syllables can be grouped together for transmission to various units of the processor.

Abstract: An error-correcting memory system includes a storage module which receives an address during a read cycle and which reads data bits and check bits at the address, and it further includes a low DC power logic circuit which corrects errors in the data bits by decoding multiple minterms from the check bits; wherein the logic circuit is comprised of: a plurality of logic gates, one for generating each of the minterms by passing a constant power dissipating current to selectively decode the check bits; a control circuit for generating a control signal that is in one state during only a small fraction of the read cycle and is otherwise in an opposite state; and an enabling circuit, coupled between the control circuit and the logic gates, for enabling their selective decoding by permitting the constant current to flow through the gates only while the control signal is in its one state.

Abstract: A method of recovering from a transmission error in a station having first and second input-output ports which are respectively coupled to two other stations in a communication network includes the steps of: receiving on the first port, messages which are separated by idle characters and regenerating same on the second port; detecting the error during the receiving step; and responding to the detection of the error by (a) transmitting silence on both the first and second ports and (b) waiting for the receipt of silence on the ports, prior to passing any further messages through the station.

Abstract: A set of titanium guide bars are shaped with inner angular finger shields to isolate designated underside edge areas of a printed circuit board being conveyed across a molten solder bath in a wave solder machine.

Abstract: A radial fin heat sink whereby a spreader plate supports a series of radial fins which are staggered around a central open cylindrical area designed to receive a flow of air by impingement. The radial fins comprise a pattern of variable lengths which follow in succession from a major length to a minor length to an intermediate length which pattern repeats around the periphery of the spreader plate.

Abstract: A parity checking system for establishing integrity of data transfer on a wide bus. Each set of "4" bus lines of a multiple line bus is passed from a driver chip to a corresponding receiver chip. An added parity driver chip senses each corresponding bit line of each driver chip to develop a set of four parity signals for comparison with corresponding parity signals from each corresponding bit line of each one of a set of receiver chips. Any discrepancy will generate a parity error signal.

Abstract: A processor forms part of a computer network wherein the processor, designated as the User Interface Processor, operates to initialize and maintain and communicate to remote diagnostic terminals for purposes of confirming integrity of the system and also for finding the location of any faults or problems in the system. The User Interface Processor involves a microprocessor unit working in conjunction with a serial communications controller, random access memory and read only memory memories, a communications input/output (I/O) system, a multiple set of timer units and a priority interrupt controller. The User Interface Processor provides interfaces to a power control card unit, an I/O subsystem (of data link processors), and a remote terminal for diagnostic intercommunication.

Abstract: A power supply system comprises several power supplies, each of which has output terminals that are coupled in parallel to supply respective DC output currents at the same time to a single load. Each power supply also has a branch of a control circuit, and each branch from every supply is coupled in parallel to thereby form a complete control circuit. In these branches, control currents flow that cause the respective output currents from the several power supplies to equalize. Each power supply also has a circuit for automatically turning the supply off independent of the other power supplies when a component in the supply fails; and under such conditions, a switch in the control circuit branch of the failing supply automatically opens which prevents control current from flowing therein and enables the remaining supplies to share the added load.

Abstract: An error-correcting memory system includes a storage module which receives an address and which reads data bits and check bits at the address, and it further includes a zero DC power gate array which corrects errors in the data bits by decoding multiple minterms from the check bits; wherein the gate array is comprised of: a plurality of capacitors, one for each of the minterms; a control circuit for generating a control signal that is in one state when the minterms are to be detected and is otherwise in an opposite state; a charging circuit, coupled between the control circuit and the capacitors, for charging all of the capacitors only when the control signal is in its opposite state; and a discharging circuit, coupled between the control circuit and the capacitors, for indicating the presence of the minterms by selectively discharging the capacitors as a selectable decode of the check bits only when the control signal is in its one state.

Abstract: A leak tolerant cooling system, for cooling electrical components with a liquid comprises: a frame holding a plurality of printed circuit boards, each of which have electrical components attached thereto; a top reservoir, mounted on the frame above the boards, for holding the liquid at atmospheric pressure; a conduit, coupled to the top reservoir and the boards, for conveying the liquid in a downward direction from the top reservoir over the components, the conduit being airtight in the absence of a leak therein; a bottom reservoir, coupled to the conduit below the boards, for receiving the liquid plus any air due to leaks from the conduit, the bottom reservoir being airtight except for a valve which opens in response to a valve control signal; a pump, coupled to the bottom reservoir, for sucking the liquid and air through the conduit at subatmospheric pressures in response to a pump control signal, and for simultaneously returning the liquid to the top reservoir; and a control circuit for generating the pump

Abstract: An integrated circuit having improved testability for defects includes a group of logic gates having respective input terminals and output terminals; a conductor that intercouples the output terminal of one logic gate in the group to respective input terminals on the remaining logic gates; a first via contact which, in the absence of a defect, couples the conductor through a first resistive device to a low voltage bus; a parasitic capacitor which couples the conductor to a high voltage bus; and a second via contact which, in the absence of a defect, couples the conductor through a second resistive device to the high voltage bus.

Abstract: A maintenance processor forms part of a computer network wherein the processor (also designated as the User Interface Processor) operates to initialize and maintain and communicate to remote diagnostic terminals for purposes of confirming integrity of the system and also for displaying data for locating any faults or problems in the network. The maintenance subsystem initiates start-up and self-test routines in a sequenced order for establishing the integrity of the units in the network. The subsystem includes means for testing two types of subsystems, that is, one having I/O controllers with self-test capability and another subsystem having I/O controllers without self-test capability. The UIP provides means for complete control of the network. It can interface the network to a remote service center where all operations such as power-up and initialization can be also effectuated.

Abstract: A three-state logic circuit comprising a logic gate on a semiconductor chip which includes first and second conductors, respective resistors connected to the conductors, terminals for receiving input signals, and transistors for generating complementary output signals on the first and second conductors by passing respective currents through the resistors as a logical function of the input signals with the output signals having high and low voltage levels V.sub.H and V.sub.L ; a control circuit on the chip having a first terminal connected to the first conductor, a second terminal connected to the second conductor, and a control terminal for receiving a control signal; a switching circuit within the control circuit which responds to the control signal by passing identical control currents through the respective resistors and into the first and second terminals to thereby lower the voltage levels on both the first and second conductors by at least V.sub.H -V.sub.

Abstract: An integrated circuit package is fabricated by assembling a stack which is comprised of a plurality of thin flat epoxy-glass layers, adhesive layers between the epoxy-glass layers, and a staircase-shaped cavity. This cavity extends from an outer epoxy-glass layer to an internal epoxy-glass layer and goes parallel along a portion of the flat surface of the internal epoxy-glass layer and then penetrates through it. Conductors lie on the internal epoxy-glass layer, including bonding pads on the flat surface portions. After the stack is assembled, a plug is inserted into its cavity. This plug is thermoplastic; and it fits snugly into the cavity and extends over a larger area outside the cavity. While the plug is in the cavity, the stack is laminated at a temperature and pressure which causes the plug to soften and conform to the exact shape of the cavity. This dams the adhesive from flowing onto the bonding pads.

Abstract: In an integrated circuit package of the type in which multiple conductors are bonded between an integrated circuit chip and the body of the package, wire bonds are tested for defects by a method which includes the steps of: placing the integrated circuit package in a magnetic field; generating respective currents through the conductors while the package is in the field to thereupon induce a magnetic force; and monitoring the current through the conductors to determine if a bond breaks under the force and causes the current through it to stop.