Patents Represented by Attorney Laurence J. Marhoefer
  • Patent number: 4726036
    Abstract: The weights of least mean square (LMS) adaptive filter are updated with a different set of taps than are used to form the output of the adaptive filter in the adaptive processing device of the present invention. As a result of performing the multiplications and sums required for the filter operation simultaneously, an integral number of clock cycle delays appear in the narrowband and error feedback channels. The number of taps of the tapped delay line of the invention are increased, whereby the increased delay through the delay line may be used to compensate for a delay through the filter of an integral number of clock delay cycles. Instantaneous weight updating in accordance with the signal being utilized, may then be achieved at a clock rate frequency that is ten times or more greater than prior art adaptive filters.
    Type: Grant
    Filed: March 26, 1987
    Date of Patent: February 16, 1988
    Assignee: Unisys Corporation
    Inventors: Laurence D. Sawyer, Patrick J. Smith
  • Patent number: 4725940
    Abstract: A pair of quantized duty ratio proportional-integral-differential (PID) converters are coupled to provide power sharing to a load. One of the converters is a master and the other is a slave, and a PID controller is coupled to both of the converters. The PID controller also supplies two digital offset signals to the converters during normal operation, which insures load sharing by control of the duty ratio of the converters. If one of the converters fails, a sensor control unit switches control to the other unit and the digital offset signal goes to zero.
    Type: Grant
    Filed: June 10, 1987
    Date of Patent: February 16, 1988
    Assignee: Unisys Corporation
    Inventor: Christopher P. Henze
  • Patent number: 4726025
    Abstract: A timing generator and verifier is provided in which a PROM stores the timing constants that are employed by the generator. An address counter, which is driven by a clock timer, cycles through an associated portion of the PROM to provide a sequence of output signals which represent timing for a particular mode. If a different mode is selected, the address counter selects a different sequence of output bits. During Normal mode the address counter operates on a cyclic basis driven by a fixed frequency free running master clock. In Verify mode the address counter is stepped by the Host computer. The outputs of the PROM are coupled through a buffer and logic section, where the outputs may be modified before being coupled to an adder which accumulates a checksum based on the outputs of all of the bits for a particular selected timing.
    Type: Grant
    Filed: October 16, 1985
    Date of Patent: February 16, 1988
    Assignee: Sperry Corporation
    Inventors: Katherine A. Splett, Steven H. Karban, Gerald L. Brown
  • Patent number: 4726035
    Abstract: The reference channel, the narrowband channel, and the error feedback channel are all constructed with analog components, while the adaptive processor is constructed with digital components. Unavoidable analog time delays in the narrowband and the error feedback channels are compensated for in the digital adaptive processor. The adaptive line enhancer described herein employs a local oscillator signal which is mixed with the input signal in a reference channel, which is subsequently converted to a digital signal. A digitized reference signal is supplied to an adaptive filter as an input signal. The adjustable weight values of the adaptive filter are adjusted by a feedback digitized signal. The output signal is derived from the subtraction of a narrowband analog signal, which is derived from the adaptive filter. The error feedback signal is split off of the output signal, mixed with the local oscillator signal, and supplied to the weight update mechanisms.
    Type: Grant
    Filed: March 26, 1987
    Date of Patent: February 16, 1988
    Assignee: Unisys Corporation
    Inventors: Scott R. Bullock, Patrick J. Smith
  • Patent number: 4723242
    Abstract: A digital system employing adaptive voting circuitry to improve its fault-tolerance receives an input data bit from each of a number of input data sources. The adaptive voting circuitry has a separate section for each of the input devices which has a weight register that stores an initial weight value which determines the voting strength of the associated input device. The weight values are multiplexed through to a voting circuit which also receives the input data bits. If an input data bit is a logic "1" the weight value of the input data device that supplied this "1" signal is added to the weight values of all other input data devices that supplied "1" data bits. If the data bit from a particular input device is a logic "0", then its weight is added to the weight values for other input data devices which supplied logic "0'". Accumulative voting then takes place via adders in the voting circuit which determines whether the correct output bit should be a logic "1" or a logic "0".
    Type: Grant
    Filed: June 27, 1986
    Date of Patent: February 2, 1988
    Assignee: Sperry Corporation
    Inventors: Brian R. Larson, Donald B. Bennett, Thomas O. Wolff
  • Patent number: 4722596
    Abstract: An acousto-optic spectrum analyzer in which the dynamic range is effectively extended by detecting the frequency bands wherein the photo-detectors are saturated and providing a filter to suppress those frequencies. With this pre-filter, the entire spectrum appears to be within the dynamic range of the photo detectors. The actual spectrum can be reconstructed using the response of the suppression filter and the photo detector output.
    Type: Grant
    Filed: May 13, 1986
    Date of Patent: February 2, 1988
    Assignee: Sperry Corporation
    Inventors: Joseph H. Labrum, F. Avery Bishop
  • Patent number: 4714837
    Abstract: A high speed, edge-triggered, set/reset flip-flop of relatively simple circuit configuration which operates on small, narrow pulses.
    Type: Grant
    Filed: July 18, 1986
    Date of Patent: December 22, 1987
    Assignee: Sperry Corporation
    Inventors: Bart A. Wilson, Vaughn J. Jenkins, Dale D. Fonnesbeck
  • Patent number: 4713742
    Abstract: A DC-to-DC power converter is constructed by coupling two parallel-connected inductors in series with a DC input power source. A communication switch is connected in series of each of the inductors. One terminal of each of these switches is connected to one terminal of the input power supply, and the other terminal of both of the switches is connected to the common side of the power supply. The commutation switches are controlled so that they have a switching duty cycle that is greater than 50%. Thus, whenever one of the switches turns off or on, the other switch will remain engaged during this switching time. As a result of this construction, the sum of the currents that flow through the inductors provides an output current to the load which has a greatly reduced ripple and a more constant output current. Also, harmonics of lesser amplitude and higher frequency content are drawn from lines, reducing the size of filter components required to reduce these input-current harmonics.
    Type: Grant
    Filed: October 9, 1986
    Date of Patent: December 15, 1987
    Assignee: Sperry Corporation
    Inventor: David W. Parsley
  • Patent number: 4712024
    Abstract: A mixer circuit wherein transistors are used to drive Schottky diodes in a star configuration in order to avoid the disadvantages of transformer coupling.
    Type: Grant
    Filed: August 16, 1985
    Date of Patent: December 8, 1987
    Assignee: Sperry Corporation
    Inventors: Charles F. McGuire, David J. Weber, Gordon C. Steyaert
  • Patent number: 4712059
    Abstract: A real time, optical processor for the detection and separation of multiple frequency hop signals and which is capable of determining both the frequency and the time of arrival for all frequencies within a specified bandwidth.
    Type: Grant
    Filed: November 12, 1985
    Date of Patent: December 8, 1987
    Assignee: Sperry Corporation
    Inventor: Joseph H. Labrum
  • Patent number: 4706181
    Abstract: A power converter is provided with a pair of auxiliary windings coupled to the primary windings of the output transformer which serve as energy choke windings. An additional pair of choke windings are coupled between the input of the converter to a common terminal of the primary winding. These choke windings prevent excess voltage from appearing across the switching devices of the converter during the turn-off portions of the cycle.
    Type: Grant
    Filed: February 2, 1987
    Date of Patent: November 10, 1987
    Assignee: Unisys Corporation
    Inventor: Larry N. Mercer
  • Patent number: 4696061
    Abstract: There is disclosed an acousto-optic filtering apparatus which includes Bragg cells in the signal path and in the local oscillator reference path of the apparatus in order to permit relatively high frequency signals to be detected by a relatively low frequency detector mechanism.
    Type: Grant
    Filed: September 22, 1986
    Date of Patent: September 22, 1987
    Assignee: Sperry Corporation
    Inventor: Joseph H. Labrum
  • Patent number: 4691973
    Abstract: A superconducting pin and socket conductor is formed with a cylindrical pin of superconducting material, such as niobium, which fits into a mating superconducting cylinder, such as niobium or titanium, which is open at the top. A superconducting wire is laser welded to the bottom of the cylinder and a second niobium wire is laser welded to the top of the pin. A sleeve of a material, such as copper, aluminum, or magnesium, which at liquid helium temperatures has a much higher coefficient thermal expansion than the superconducting material, surrounds the cylinder. As a result, upon cooling the outer sleeve crimps the cylinder into a firm and uniform contact along the length of the pin.
    Type: Grant
    Filed: June 5, 1986
    Date of Patent: September 8, 1987
    Assignee: Sperry Corporation
    Inventor: Mark E. Rosheim
  • Patent number: 4692899
    Abstract: Stabilization of the propagation of storage bits around the storage loops of a Vertical Bloch Line (VBL) memory is obtained by the vapor-deposition of a nickel-iron film over the VBL structure. The film has a composition range of 65-90% nickel and a thickness of 1,000 to 10,000 Angstroms, and is deposited in a vacuum of 10.sup.-4 to 10.sup.-6 Torr to provide parallel, periodic, magnetic stripe domains, and thus potential well domains, that have a periodicity in the range of 0.1 to 1 micron. The stripe domains are oriented perpendicular to the direction of data propagation and form potential wells along the elongated direction of the storage loops.
    Type: Grant
    Filed: December 12, 1985
    Date of Patent: September 8, 1987
    Assignee: Sperry Corporation
    Inventors: David S. Lo, Stanley J. Lins
  • Patent number: 4691303
    Abstract: Refresh signals for a multiple semiconductor MOS bank memory are implemented with a refresh counter that supplies 15.6 microseconds refresh pulses so that one row of 128 row of memory bank, or of each of a group of memory banks, may be refreshed on a sequential, stepped-through basis. The occurrence of each refresh pulse is effective to refresh one row or a group of rows, providing that refresh lock-out logic does not prevent the refresh pulses signals from being applied to the memory banks. An up/down counter is initially filled to a count of eight, and counts toward zero once each time a refresh pulse occurs and the memory is busy. As long as the count has not reached zero the lock-out logic is effective, but when a count of zero occurs refresh of each new row in the sequence occurs at the 15.6 microsecond rate until the memory is no longer busy; at which time a burst of eight count up pulses is supplied to the up/down counter, and eight new rows are rapidly refreshed at 450 nanosecond intervals.
    Type: Grant
    Filed: October 31, 1985
    Date of Patent: September 1, 1987
    Assignee: Sperry Corporation
    Inventors: Reed R. Churchward, Thomas L. Krocheski
  • Patent number: 4691126
    Abstract: A synchronous clock circuit is provided on each module of an electronic digital system formed of a plurality of modules. Each clock circuit has two control pins which are used by control logic to determine whether or not the clock on a particular module is disabled, is operating as the master clock for the system, or is providing a backup function for the master clock. The common clock line is supplied through a buffer to the components on the module which require clocking. Logic circuitry on the backup clock mode insures the backup clock is in a ready condition in case there should be either failure of the master clock oscillator or if the master clock module is removed from the unit. All of the clock circuits of the different modules may be constructed in an identical manner, with the control of the function of the circuitry being provided simply by control of the logic level on the two terminals.
    Type: Grant
    Filed: August 29, 1985
    Date of Patent: September 1, 1987
    Assignee: Sperry Corporation
    Inventors: Katherine A. Splett, James A. Howe
  • Patent number: 4689559
    Abstract: A SQUID, nominally of the "hybrid" type, wherein the normally superconducting modulation coil is modified to instead be a non-superconducting material, nominally manginin, exhibits reduced long-term, or d.c., thermal response. When an alternating current waveform--rising to a nominal 130 ma. r.m.s. amplitude within a nominal 0.5 seconds and, after a nominal 100 msec. to 20 sec. duration, returning to 0 within a nominal 0.1 sec--is applied to the non-superconducting modulation coil of such a SQUID at superconducting temperature then the entire SQUID thermal response, particularly including the short-term, or a.c., SQUID thermal response, is thereafter reducible to essentially 0. The process is hypothesized to "deflux" the SQUIDs of fluxons trapped during the cool-down of superconductor within the SQUID and associated circuitry. The optimal "de-fluxing" alternating current waveform for any individual SQUID is empirically derivable.
    Type: Grant
    Filed: November 13, 1984
    Date of Patent: August 25, 1987
    Assignee: Sperry Corporation
    Inventors: Roger N. Hastings, Gerald F. Sauter, George F. Nelson
  • Patent number: 4654780
    Abstract: A parallel register-transfer mechanism has been disclosed above for use in the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expression is reduced through a series of transformations until a result is obtained. A register file is provided with several crossbar networks interconnecting the various registers in the file for simultaneous transfer of their contents.
    Type: Grant
    Filed: June 5, 1984
    Date of Patent: March 31, 1987
    Assignee: Burroughs Corporation
    Inventors: Gary L. Logsdon, Mark R. Scheevel, Brent C. Bolton
  • Patent number: 4651064
    Abstract: A video display terminal is provided with controls which permit independent adjustment of the background information and the foreground information. Each control comprises an adjustable constant current source connected to one of two branches of a differential amplifier. One branch of the differential amplifier is employed to control the background intensity and the other branch of the differential amplifier is employed to control the foreground intensity.
    Type: Grant
    Filed: September 13, 1984
    Date of Patent: March 17, 1987
    Assignee: Sperry Corporation
    Inventors: Stephen J. Parker, Clayton C. Wahlquist
  • Patent number: 4644464
    Abstract: A parallel register-transfer mechanism and control section have been disclosed above for use in a reduction process for the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expressions are reduced through a series of transformations until a result is obtained.
    Type: Grant
    Filed: June 5, 1984
    Date of Patent: February 17, 1987
    Assignee: Burroughs Corporation
    Inventors: Gary L. Logsdon, Mark R. Scheevel, Frank A. Williams, Jr.