Abstract: A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.

Abstract: An electronic device (21) switches its operation mode in accordance with the type of an installed battery pack (22). The battery pack (22) has a regulator (222), a specification-discriminating terminal (TJ), and a resistor (224), connected between the regulator (222) and the specification-discriminating terminal (TJ) and having a resistance corresponding to the specification of the incorporated battery (221). The electronic device (21) has a monitor resistor (214) connected between a terminal (TL) connected to the specification-discriminating terminal (TJ) of the battery pack (22) and ground, a discriminating circuit (212, 215, 216) for detecting a monitor voltage generated across this monitor resistor (214) to discriminate the specification of the battery (221), and a switch controller (212, 219) for switching the operation mode in accordance with the specification discriminated by the discriminating circuit (212, 215, 216).

Abstract: A method of performing trench isolation in a CMOS transistor, that produces no latch-up and results in an effective isolating structure without using an epitaxial growth process. A field oxide layer is provided on a silicon substrate to isolate an active region. A first conductivity-type well is formed at a predetermined position of the active region. A gate oxide layer, a polysilicon layer and a silicide layer are deposited in sequence. A first gate electrode and a second gate electrode are formed by lithography and etching techniques wherein the first gate electrode is on the well, and the second gate electrode is on the active region outside the well. A silicon nitride layer is deposited and etched back to form spacers on the side walls of the electrodes whereby slits are left between the field oxide layer and the spacers and between adjacent spacers. Trenches are formed by etching the silicon substrate in the slits.

Abstract: An electrophotographic development apparatus capable of maintaining the surface roughness of a developer roller thereof for a long term or even for the life span of the apparatus. The developer roller includes an elastic layer, formed on a core metal shaft, and made of a rubber elastic material with additional insulating micro-powder of 30 to 200 parts having a particle diameter in a range of 1 to 50 micrometers, where the amount of the rubber elastic material constitutes 100 parts. During a printing operation, the insulating micro-powder drops from the elastic layer as the rubber elastic material is worn, so that the developer roller can maintain its surface roughness in proportion to the particle diameter of the dropped powder.

Abstract: A snowboard has a pair of bindings for a person's footwear. Each binding includes a laterally spaced apart independently moveable pair of binding straps and latches that can be engaged in latched positions over the vamp of the footwear for binding the footwear to the snowboard. On each binding, a release strap is connected between the two latches, so that by pulling on the release strap in a direction away from the snowboard's upper surface, forces are applied to actuation members of both latches so as to release both binding straps from their latched positions.

Abstract: A word line driver has a decoder for outputting decode signals having first and second logic levels, level shifters for receiving the respective decode signals, each level shifter outputting drive signal having first and third logic levels in response to the received decode signal, the third logic level being higher than the second logic level; a pumping circuit for outputting word line activation signals, at least one of the word line activation signals having the third logic level; and groups of output circuits, each group having the output circuits connected to one of the level shifters and a word line, respectively, each of the output circuits outputting the word line activation signal to the respective word line in response to the decode signal and the drive signal.

Abstract: A method of fabricating memory cells with buried bit lines. In this method, a pad oxide layer is formed on a first conductivity-type silicon substrate. A photoresist layer is formed on the pad oxide layer while exposing predetermined areas of channels. A thick oxide layer is deposited by liquid phase deposition (LPD). The photoresist layer is removed. Second conductivity-type impurities are implanted to form source-drain electrodes using the thick oxide layer as a mask. The thick oxide layer and the pad oxide layer are removed to form bit lines and then word lines are formed crossing the bit lines, whereby the structure with buried bit lines and an array of memory cells is completed.

Abstract: A code-division multiple-access receiver carries out the following steps whenever it recognizes a symbol boundary in the received baseband signal. First, using the despreading code of the relevant station, it estimates the value of the symbol. Next, using the spreading code of the station, it estimates an interference signal, and modifies the baseband signal by subtracting the interference signal. These steps can be iterated for each symbol. The iterations can be organized into stages, with estimated symbol values from one stage passed to the next stage for use in estimating new symbol values in that next stage. At the end, the remaining baseband signal can be used to adjust the final estimated symbol values.

Abstract: A dynamic RAM having a TAG address holding circuit in a TAG block in correspondence with one of a plurality of sub-arrays to hold the lower bits of an X (row) address. A block control circuit in the TAG block determines a "Hit" or "Miss" in accordance with the held address and a new X address in response to the sub-address and outputs a TAG determination signal. In response to the TAG judgment signal, a sub-array control circuit transfers a signal for access to the TAG block and a column sense amplifier. The column sense amplifier is utilized as a cache and data latched in the column sense amplifier are read out on a data bus when a "Hit" is determined.

Abstract: A coherent phase-shift keying (PSK) detector in a receiver generates an unmodulated carrier signal, without attempting to synchronize the unmodulated carrier signal in frequency or phase to the carrier employed at the PSK transmitter. The instantaneous phase of the received PSK signal is detected with reference to the unmodulated carrier signal to create an instantaneous phase signal. Phase rotation due to frequency offset between the two carrier signals is detected and removed from the instantaneous phase signal, then a remaining phase offset is detected and removed. Data are recovered from the resulting instantaneous phase signal.

Abstract: There is provided a resonant circuit incorporating at least a coil L1 therein and a switching circuit for oscillation is connected to the resonant circuit and voltage doubler rectifier circuits 31 and 32 including capacitors C11, C12, C21 and C22 and diodes D11, D12, D21 and D22 are also connected to the resonant circuit. When the switching circuit for oscillation is turned on and off, the resonant voltage V.sub.L1 is generated in the resonant circuit and rectified with a voltage doubler amplitude by the voltage doubler rectifier circuits 31 and 32. A switching circuit for output changing over is connected to zero voltage terminals of the diodes D11 and D21 in the voltage doubler rectifier circuits 31 and 32. When the switching circuit for output changing over is turned on and off, an output voltage is selectively generated at output terminals OUT1 and OUT2.

Abstract: A clock signal hull detector includes a signal level monitor for detecting an extraordinary condition in which the clock signal to be monitored is stuck at either a high level or a low level and a turning point number monitor for detecting an extraordinary condition in which the clock signal changes its level between the high and low levels with high frequency. The outputs of the signal level monitor and the turning point number monitor are fed to a fault judgment portion, which delivers an output according to the extraordinary conditions. The output of the fault judgment portion is then fed to a counting portion at which a fault judgment signal is fed to its output when its input signal is counted to a predetermined value or above.

Abstract: An optical device is disclosed which comprises a base including a lower cylindrical base member having a common central line and a first diameter and having top and bottom surfaces, a first electrode layer formed on the top surface of the lower base member, a dielectric layer formed on the first electrode, a second electrode layer formed on the dielectric layer, and an upper base member formed on the second electrode layer, the upper base member including a first cylindrical member having the common central line and the first diameter and having top and bottom surfaces, the bottom surface of the first cylindrical member faced on the second electrode layer and a second cylindrical member having the common central line and a second diameter smaller than the first diameter and having a top surface and a bottom surface faced on the top surface of the first cylindrical member; elongated leads supported by the base, the leads being elongated so as to protrude from the bottom surface of the lower base member; a ring

Abstract: A method for making a nonvolatile memory device having a field effect transistor for storing information, and a Schottky diode in series with the field effect transistor. The field effect transistor includes source and drain regions in a semiconductor substrate, with a channel region interposed between them and a gate electrode above the channel region. A ferroelectric gate film is sandwiched between the channel region and the gate electrode. In the method, a conductive barrier meterial is deposited in contact with the source region of the field effect transistor to make the Schottky diode. In reading information from the memory device, voltage is applied to a serial circuit consisting of the field effect transistor and the Schottky diode to turn the Schottky diode on.

Abstract: A handle stem fixing device in a bicycle includes a stem-binding cylinder 30 fitted on an upper portion of a fork stem 10 and a screw cap 4 engaged with an upper portion of the fork stem 10, wherein a thread is formed on an outer surface of the fork stem 10, and the screw cap 4 has a bore with internal thread. The cap 4 can be engaged with the thread of the fork stem when the upper portion of the fork stem 10 projects out from an upper end of the stem-binding cylinder 30. While the screw cap 4 is tightened, the 10 stem-binding cylinder 30 is depressed in an axial direction thereof by the cap 4 and is fixed on the upper portion of the fork stem 10.

Abstract: In a handle stem fixing device in a bicycle wherein a fork stem 10 is rotatably inserted into a head pipe 20 of a frame 2, the upper portion of the fork stem 10 projects out from the upper end of the head pipe 20 and a stem-binding cylinder 30 is fixed on the upper portion of the fork stem 10 so as not to rotate. Many small protrusions are formed on the outer surface of the fork stem 10 where is pressed by the stem-binding cylinder 30. The coefficient of friction between contact surfaces of the fork stem 10 and the stem-binding cylinder 30 increases because of the protrusions. The coupling power acting between the fork stem 10 and the stem-binding cylinder 30 can thus be improved.

Abstract: A window-based ATM cell stream regulator composed of a means for detecting to which connection an arriving cell belongs among a plurality of connections, a detector for detecting when the cell arrived within the same connection based on its arrival time, a window start time stored in a memory and a predetermined window section length stored therein and a memory for storing the updated number of counted cells and the window start time.