Abstract: A surface-emitting light-emitting diode having increased light emission is provided.

Abstract: An improved capacitor for a semiconductor memory device for preventing a bridge between storage electrodes and enlarging a surface area of a capacitor can be manufactured by forming a second insulating layer on a first insulating layer including a plug, etching the second insulating layer to form a storage electrode opening by using a storage electrode formation mask until the plug and a part of the first insulating layer are exposed, forming a conductive spacer on the sidewalls of the storage electrode opening to connect electrically to the plug, and forming an HSG (hemispherical grain) layer on the surfaces of the conductive spacers and the plug. A capacitor according to the present invention enables the HSG layer to grow on an internal wall of a storage electrode, thereby preventing a micro-bridge between storage electrodes resulting from abnormal growth or over-growth of the HSG layer.

Abstract: A semiconductor device having a fuse includes a first insulating layer that has a predetermined metal wire, a second insulating layer that has a heat blocking layer being positioned over the predetermined metal wire, and an upper layer. The upper layer includes a deposition structure having a fuse metal layer and a wiring metal layer. The fuse metal layer has a fuse pattern that is used as a fuse and is exposed via a fuse window in the upper layer. The fuse pattern is electrically connected to the wiring metal layer. The semiconductor device is designed so that the heat blocking layer is larger than the fuse window and is positioned under the fuse metal layer. The semiconductor device is further constructed with the fuse metal layer being formed on the metal wire, thereby preventing limitations in the layout arrangement or in the fabrication process in order to achieve a high degree of integration. A method of manufacturing the above semiconductor device is also described.

Abstract: A semiconductor device having a double layer type anti-reflective layer, which can reduce reflectivity in a photolithography process using, for example, an exposure light source of a 193 nm wavelength region and which can suppress intermixing at the boundary between an anti-reflective layer and a photoresist layer, and a fabrication method of the semiconductor device are disclosed. The semiconductor device includes an underlying layer having a high reflectivity formed on a semiconductor substrate, a double layer type anti-reflective layer formed of a nitride layer and a layer formed using only hydrocarbon-based gas on the underlying layer, and a photoresist layer formed on the double layer type anti-reflective layer. In the double layer type anti-reflective layer, the nitride layer and the layer formed using only hydrocarbon-based gas can be sequentially stacked. Also, it is possible that the layer formed using only hydrocarbon-based gas and the nitride layer are sequentially stacked.

Abstract: A six-axes force-moment measuring apparatus includes a mechanical structure having sensors installed at predetermined positions on the mechanical structure for measuring tensile and compressive forces applied to each axis. The output signal from the sensors is processed and analyzed to determine the forces and/or moments applied to the mechanical structure. The six-axes force-moment measuring apparatus is readily constructed and repaired, and is capable of supporting large loads.

Abstract: An LED lamp apparatus comprises a plurality of LED lamps including at least one LED chip mounted on a printed circuit board, on which a driver circuit and/or a control circuit are provided in a printed circuit pattern to drive and/or control the LED chip, at least one female lead electrode terminal constituted as a hollow coupling pin to be inserted into at least one through holes for at least one power source terminal and a control signal tenninal and a body made into a unit of the LED lamp, using transparent or translucent epoxy resin, in which the LED lamps are arranged in series or parallel to form a predetermined block, the driver and control circuits are respectively or collectively provided in the block, and one block or a plurality of blocks arranged in series or parallel are made into a body to be molded into transparent or translucent epoxy resin to form a case.

Abstract: A method of forming a contact hole for a semiconductor device, and a method of forming a capacitor for a semiconductor device using the same. An interlayer dielectric layer, a contact mask material layer including of a material having a high etching selectivity with respect to the interlayer dielectric layer, an anti-reflection layer, and a photoresist layer, are formed on a semiconductor substrate. A photoresist pattern is formed from the photoresist layer to expose part of the anti-reflection layer, and a flow process is performed on the photoresist pattern to expose even a smaller amount of the anti-reflection layer. The anti-reflection layer and the contact mask material layer are then etched to expose part of the interlayer dielectric layer, and the interlayer dielectric layer is etched to form a contact hole.

Abstract: A capacitance gauge tracking apparatus used for an exposure system for manufacturing a semiconductor device, a method for tracking a surface of the semiconductor device, a leveling apparatus and a leveling method are provided. The capacitance gauge tracking apparatus includes a ground unit, a probe unit and a gauge unit. The ground unit is connected to a semiconductor substrate. The probe unit is spaced apart from the surface of the semiconductor substrate to be tracked and a constant current of at least two frequency bands is applied to the probe unit. A constant current of a low frequency is applied to the probe unit to thereby perform global leveling by global tracking of the entire surface of the semiconductor substrate and a constant current of a high frequency is applied to the probe unit to thereby perform local leveling by local tracking on the semiconductor substrate.

Abstract: A method for manufacturing a photoresist pattern that defines an opening having a small size, and a method for manufacturing a semiconductor device using the same are provided. A photoresist pattern defining the opening can be formed using a photoresist composition that includes either polymer mixture I containing a polymer A in which an acid-labile di-alkyl malonate group is pendant to the polymer backbone, and a polymer B in which a group that thermally decomposes at a temperature lower than the glass transition temperature of the polymer B itself is pendant to the polymer backbone, or polymer mixture II containing the polymer B and a polymer C including a (meth)acrylate as a monomer, as a main component. The size of the opening then can be reduced by thermal flowing the photoresist pattern.

Abstract: A method of fabricating a contact window of a semiconductor device, whereby a contact window of a semiconductor device is increased to offset any incline phenomenom and avoid unwanted increase in contact sheet resistance, comprises forming a lower conductive member on a semiconductor substrate, forming a first insulative film on the lower conductive member, the first insulative film being formed of an insulative material doped with impurities at a first level of concentration, the first insulative film having a wet etch rate that is proportional to the level of concentration of impurities, forming a second insulative film on the first insulative film, the second insulative film being formed of an insulative material doped with impurities at a second level of concentration that is lower than the first level of concentration of impurities, the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities, opening a contact window and exposing the lower condu

Abstract: A method for forming alignment keys on the scribe line areas of a semiconductor wafer. An etch blocking layer is used to reduce the depth of the channels forming the alignment key. One of the layers of material deposited on the semiconductor wafer to form integrated circuit devices on the wafer may be used as the etch blocking layer. A portion of this layer of material may be left intact on the scribe line areas during the manufacturing process. The subsequently deposited layers have an etch selectivity with respect to the etch blocking layer and the subsequently deposited layers are etched down to the etch blocking layer to form the alignment keys.

Abstract: A method of constructing a multi-layered wiring system of a semiconductor device is provided, wherein the method includes steps of: sequentially forming first and second conductive layers on a semiconductor unit board having the first insulation layer; forming an anti-reflective layer in a structure of Ti/TiN deposition layers by means of a sputter device having a collimator on the second conductive layer; selectively etching predetermined portions of the anti-reflective layer, the second conductive layer and the first conductive layer to expose predetermined portions of the first insulation layer to form a metal wire; forming the second insulation layer at the front side of the aforementioned structure; forming a via hole by dry-etching predetermined portions of the second insulation layer and the anti-reflective layer to expose predetermined portions on the surface of the metal wire with tapered parts of anti-reflective layer remaining along the edges of the bottom thereof; performing a wet etching process

Abstract: A method for forming contact plugs and simultaneously planarizing a substrate surface in an integrated circuit. Initially, a conductive structure is formed on a semiconductor substrate having a plurality of diffusion regions therein. A first insulating layer is formed over the semiconductor substrate including the conductive structure. The first insulating layer is etched using a contact hole forming mask to form a contact hole. A conductive layer is formed on the first insulating layer filling up the contact hole with the conductive layer. The conductive layer is etched until an upper surface of the first insulating layer is exposed. A second insulating layer is formed over the first insulating layer. A contact plug free of voids is formed and simultaneously a substrate surface is planarized by planarization-etching the second and first insulating layers.

Abstract: A wide range voltage controlled oscillator including a voltage-to-current conversion unit generating a control current responsive to a control voltage, and an offset current generation unit generating an offset current. The offset current generation unit is responsive to the control voltage and, at certain times, is responsive to a reference voltage. An adding unit adds the control current to the offset current, and generates an oscillation control current. An oscillation unit generates the oscillation signal responsive to the oscillation control current.

Abstract: A semiconductor memory device capable of operating normally even when a failed memory cell remains after repair. The semiconductor memory device includes a plurality of memory cell array blocks, and address decoding circuitry for receiving an address and for accessing good memory cell array blocks and skipping failed memory cell array blocks.