Patents Represented by Attorney Law Offices of Michael Dryja
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Patent number: 7307620Abstract: A one-handed thumb-supported mobile input device for a computing device includes an input mechanism and a thumb loop or an elastic band in which a thumb of a hand may be inserted. The thumb loop or elastic band is attached to an adjustable thumb loop holder that is enclosed within a thumb loop holder and is adjustable with respect to the thin sections of the input mechanism. The thumb loop holder is attached to one of the sections of the input mechanism. The input mechanism has a folded position and an unfolded position, and includes a number of thin sections containing a number of keys, and which may have one or more folds. The device may further include a display mechanism having a folded position and an unfolded position, and including a thin section containing a display and that is foldable with respect to the sections of the input mechanism.Type: GrantFiled: February 4, 2005Date of Patent: December 11, 2007Inventor: Shakoor N. Siddeeq
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Patent number: 7299245Abstract: Determining similarity among recipes is disclosed. A computer-implemented method of one embodiment of the invention receives a first recipe. The method determines one or more second recipes that are similar to the first recipe, and then outputs the one or more second recipes. The second recipes may be determined as being similar to the first recipe based on one or more different factors in one embodiment. Such factors may include: a weighted ingredient coefficient; a weighted same-type coefficient taking into account whether recipes are of the same type; a weighted same-title words coefficient taking into account the extent to which non-common title words of one recipe are also within the titles of other recipes; a weighted shared-keywords coefficient taking into account shared keywords among recipes; and, a weighted shared-ingredients coefficient taking into account the extent to which ingredients are shared among recipes.Type: GrantFiled: January 18, 2004Date of Patent: November 20, 2007Assignee: Allrecipes.comInventor: Timothy D. Hunt
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Patent number: 7133021Abstract: A finger-fitting pointing device is disclosed. There is at least one housing. Each housing can be fabricated from a flexible, glove-like material, and fits a finger of a user. A click sensor is disposed in the underside of each housing, and is actuated by the user pressing the underside of the housing with the inserted finger against an external surface. An optical sensor is also disposed within the surface of a housing, and detects relative movement of this surface against an external surface, as caused by relative movement of the user's finger.Type: GrantFiled: June 9, 2001Date of Patent: November 7, 2006Inventor: Francis F. Coghan, IV
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Patent number: 6970157Abstract: A wearable computing, input, and display device is disclosed. One embodiment of the invention includes a band wrappable around a wrist of a user, one or more input mechanisms, a display mechanism, and a computing mechanism. The input mechanisms are attached to the band and have recessed and extended positions. In the recessed position, the input mechanisms are positioned under the wrist of the user. In the extended position, the input mechanisms are substantially positioned at the user's fingertips. The display mechanism is attached to the band such that it is over the wrist of the user, whereas the computing mechanism is attached to the band and operably coupled to the input and display mechanisms. In an alternate embodiment, the display mechanism is additionally rotatable from a flat position to a raised position, and vice-versa, where the raised position is user controlled for optimal viewing by the user.Type: GrantFiled: April 19, 2003Date of Patent: November 29, 2005Assignee: QuadTri Technologies, LLCInventor: Shakoor N. Siddeeq
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Patent number: 6910108Abstract: A system and method of partitioning a multiprocessor or multinode computer system containing two or more partitions each of which contain at least three nodes or processors and a central hardware device communicating with a requestor node or processor, a target node or processor and at least one additional node or processor in the partition. The multiprocessor system architecture allows for partitioning resources to define separate subsystems capable of running different operating systems simultaneously. The method operates with the central device, a tag and address crossbar system, which transmits requests for data from the requestor node to the target node, but not to any of the additional nodes or processors which are not defined as part of a given partition. The method provides steps of assignment of definitions to physical ports with the central device corresponding with desired partitioning of resources within the system.Type: GrantFiled: January 9, 2002Date of Patent: June 21, 2005Assignee: International Business Machines CorporationInventors: Wayne A. Downer, Bruce M. Gilbert, Thomas D. Lovett
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Patent number: 6880013Abstract: Network or mobile clients are enabled to keep their connections open across shutdowns and reboots of computer systems. Transactions are suspended while the client system is down, and resumed when it comes back up, allowing end-users to perform orderly shutdowns of their systems (especially useful to save battery power on mobile systems) without risk of losing transactions on open TCP connections.Type: GrantFiled: December 29, 2000Date of Patent: April 12, 2005Assignee: International Business Machines CorporationInventor: Vivek Kashyap
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Patent number: 6871296Abstract: The present invention provides a method, system and apparatus by which TCP connections may be failed-over from one system to another within a highly available network service, and appear transparent to the remote client. The connection state and ownership information of a system is broadcast within the network, so that if a first system crashes while running an application, a predetermined take-over policy causes a peer system to assume connection without loss of data such that a permanent connection has been established from the client's point of view. After the failed system has been restored to a normal state, new connections are established by the first system.Type: GrantFiled: December 29, 2000Date of Patent: March 22, 2005Assignee: International Business Machines CorporationInventor: Vivek Kashyap
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Interruption handler-operating system dialog for operating system handling of hardware interruptions
Patent number: 6851006Abstract: Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling such an interruption, and information regarding the interruption, are stored by the interruption handler in a storage accessible by the operating system. The interruption handler calls the operating system at a predetermined interruption handling point thereof, for the operating system to handle the interruption. The handler then determines whether the operating system handled the interruption according to the recommendation.Type: GrantFiled: August 25, 2001Date of Patent: February 1, 2005Assignee: International Business Machines CorporationInventor: Daryl V. McDaniel -
Patent number: 6848026Abstract: Caching memory contents into cache partitions based on their locations is disclosed. A location of a line of memory to be cached in a cache is determined. The cache is partitioned into a number of cache sections. The section for the line of memory is determined based on the location of the line of memory as applied against a memory line location-dependent allocation policy. The line of memory is then stored in the section of the cache determined.Type: GrantFiled: November 9, 2001Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Donald R. DeSota, Adrian C. Moga, Carl E. Love, Russell M. Clapp
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Patent number: 6829679Abstract: Caching memory contents differently based on the region to which the memory has been partitioned or allocated is disclosed. A first region of a first line of memory to be cached is determined. The memory has a number of regions, including the first region, over which the lines of memory, including the first line, are partitioned. Each region has a first variable having a corresponding second variable. If the first variable for any region is greater than its corresponding second variable, one such region is selected as a second region. A line from the lines of the memory currently stored in the cache and partitioned to the second region is selected as the second line. The second line is replaced with the first line in the cache, the first variable for the second region is decremented, and the first variable for the first region is incremented.Type: GrantFiled: November 9, 2001Date of Patent: December 7, 2004Assignee: International Business Machines CorporationInventors: Donald R. DeSota, Thomas D. Lovett
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Patent number: 6826754Abstract: An improved data structure handles locks and other mutual exclusion (mutex) mechanisms during a “panic” shutdown of the system such as when the system “hangs”. Existing mutex data structures include an identifier of the engine/processor, the thread, or the processes acquiring the mutex. The improved mutex data structure further includes an indicator of whether the mutex was acquired before or after the panic (pre-panic or post-panic), preferably as a modification of the engineID after the panic is initiated such as by assigning the engines different engineIDs post-panic. The method checks mutexes to determine whether they were acquired pre- or post-panic mutexes. During a panic, alternative mutex handling routines free (release) pre-panic mutexes and shoot down the processors owning these mutexes. The data structure and method are generally useful in state transitions of the system, its engines/processors, and its processes and threads.Type: GrantFiled: September 29, 2000Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventor: Douglas R. Miller
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Patent number: 6823498Abstract: A masterless approach for binding building blocks to partitions is disclosed. Other blocks are first sent a first physical port identifier indicating a block's physical location, and a first partition identifier indicating the block's partition. Second physical port identifiers and second partition identifiers are received from the other blocks. The first physical port identifier and the second physical port identifiers of a subset of the other blocks are then sent to the subset, the second partition identifiers of the subset being equal to the first partition identifier. The first physical port identifier and the second physical port identifiers of the subset are also received from each block of the subset. A first logical port identifier indicating the block's logical location is sent to the subset, and second logical port identifiers are received from the subset. The block joins the partition indicated by the first partition identifier.Type: GrantFiled: January 9, 2002Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Wayne A. Downer, Bruce M. Gilbert, Thomas D. Lovett, Mehul M. Shah
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Patent number: 6807586Abstract: A method and apparatus for a mutiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of mutiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).Type: GrantFiled: January 9, 2002Date of Patent: October 19, 2004Assignee: International Business Machines CorporationInventors: Thomas B. Berg, Adrian C. Moga, Dale A. Beyer
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Patent number: 6785779Abstract: A method of classification of transaction address conflicts in a computer system for ensuring efficient ordering in a two-level snoopy cache architecture. The disclosure provides a method of classification and handling of address conflicts within a system to minimize the impact that address ordering places in a multiprocessor system with multiple memory control agents generating potentially conflicting addresses. A set of classification for each potential transaction conflict is provided against which decisions are provided which identifies the earliest point at which a subsequent transaction within the system may proceed to the same address identified by a previous transaction in the system. Classification of transactions are provided in several high level classes which define how such transactions within the system are handled based on the method disclosed.Type: GrantFiled: January 9, 2002Date of Patent: August 31, 2004Assignee: International Business Machines CompanyInventors: Thomas B. Berg, Stacey G. Lloyd
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Patent number: 6785888Abstract: Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.Type: GrantFiled: February 24, 1998Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Paul E. McKenney, Phillip E. Krueger, Stuart A. Friedberg, Brent A. Kingsbury
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Patent number: 6779090Abstract: A spin lock for shared memory is disclosed. A lock flag for a lock on a memory section is attempted to be set. If the lock flag is successfully set, the lock on the memory section is held so that the memory section may be processed. Upon being ready to release the lock on the memory section, and in response to determining that one or more units are spinning for the lock on the memory section, one of the spinning units is selected, and a spin flag for the selected unit is reset. If no units are spinning for the lock, however, the lock flag for the lock is reset.Type: GrantFiled: May 21, 2002Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Paul E. McKenney, William L. Irwin, III, Swaminathan Sivasubramanian, John G. Stultz
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Patent number: 6775743Abstract: The special handling of multiple identical requests for the content during content caching is disclosed. A request for content, such as a web page request received from a client, is received. At least one of two actions is then performed. First, in response to determining that the content is cacheable and that a previous request for the content has already been forwarded to a server responsible for the content, such as a web server, the request is not processed until a response to the previous request is received. Second, in response to determining that the content is non-cacheable, the request is forwarded to the server responsible for the content.Type: GrantFiled: September 12, 2001Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventor: Burzin Patel
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Patent number: 6768650Abstract: A decoupling capacitor structure and its use in a circuit board mounting an ASIC is provided. The decoupling capacitor structure is arranged so that parasitic inductance caused by the connection to the decoupling capacitor and the decoupling capacitor itself is reduced. The circuit boards include at least two voltage planes. An ASIC having active device(s) is connected to one face of the circuit board. A decoupling capacitor structure is provided having at least two conductive plates in a dielectric material and is connected directly or indirectly to the ASIC. Vias extend from the conductive plates through the dielectric material to connect to circuit board vias on a second face of the printed circuit board or to the ASIC. The decoupling capacitor vias are parallel to each other; and each via connected to one conductive plate is located adjacent a via connected to another conductive plate to minimize voltage deviation.Type: GrantFiled: February 7, 2002Date of Patent: July 27, 2004Assignee: International Business Machines CorporationInventor: William John Devey
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Patent number: 6724315Abstract: Identifying the mounting locations of sub-systems in mounting units, such as rack cabinets, is disclosed. A mounting unit has a number of sub-system mounting locations. Each of one or more sub-systems is mounted in a corresponding sub-system mounting location of the cabinet. Each of one or more active indicators has an indicator mounting position on either the mounting unit or one of the sub-systems. Each of one or more sensors has a sensor mounting position similarly on either the mounting unit or one of the sub-systems, and also detects indication from a corresponding active indicator. The active indicators and the sensors cooperatively function to identify the corresponding sub-system mounting location of each sub-system in the mounting unit.Type: GrantFiled: January 2, 2002Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventor: Wayne A. Downer
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Patent number: 6701403Abstract: Non-volatile memory access, such as firmware access by a service processor, is disclosed. The service processor asserts a controller signal to select either a first non-volatile memory, or a second non-volatile memory. The first non-volatile memory is located behind a first bridge controller and is otherwise accessible by the service processor. The second non-volatile memory is located behind a second bridge controller and is otherwise accessible only by a processor other than the service processor. The service processor then access the selected non-volatile memory, via a bus communicatively coupled to both the non-volatile memories.Type: GrantFiled: October 1, 2001Date of Patent: March 2, 2004Assignee: International Business Machines CorporationInventors: Richard A. Lary, Daniel H. Bax