Abstract: A layer of polycrystalline silicon is coated with a masking layer leaving at least one edge of the silicon layer exposed. A P-type dopant is diffused into the exposed edge of the silicon layer so that the dopant diffuses laterally along the silicon layer a desired distance. The masking layer is then removed and the undoped portion of the silicon layer is removed by an etchant which does not etch the doped portion of the silicon layer. This leaves the narrow strip of the doped silicon which can be used as the gate electrode of an MOS transistor and/or as an interconnection in an integrated circuit. Since the lateral diffusion of the dopant can be accurately controlled, narrow strips of the doped silicon can be achieved.

Abstract: A semiconductor device includes a region of polycrystalline silicon on a portion of the surface of a body of semiconductor material. A layer of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer.

Abstract: A short channel MOS transistor and the method for fabricating same is described wherein the dopant concentrations of the source and drain regions are maintained at different levels of conductivity modifiers. The method described teaches first doping the source region while maintaining the drain region masked and then doping both the source and drain regions.

Abstract: A monolithic semiconductor-on-insulator device includes silicon islands in spaced relation on the surface of an insulating substrate, with the spaces between the islands occupied by a passivating material which comprises a layer of a semi-insulating material having finite but low conductivity on the surface of the substrate and extending between adjacent islands into contiguous relation with the side surfaces thereof. The surface of the semi-insulating material has a layer of insulating silicon dioxide thereon. The conductivity of the semi-insulating material is such that charge does not accumulate in this material adjacent to the side edges of the islands, but its conductivity is low enough so that leakage currents between devices remain below an amount which would render the circuit which uses the device non-operative.

Abstract: The radiation resistance of an MOS transistor is improved by making the transistor in a manner such that, after the gate insulation layer is formed, all further steps are carried out at a relatively low temperature, i.e., less than about 900.degree. C. The source and drain regions are preferably formed by ion implantation with very little or no post implant thermal activation, and the metallization is applied by low temperature techniques.

Abstract: A diffusion furnace having particular utility in the processing of SOS devices wherein a temperature gradient, per unit length of furnace tube, is provided at a section of a reaction tube extending between the furnace and the scavenger and load-unload chambers in order to minimize the thermal shock to which a sapphire wafer may be subject, either at the commencement of processing when the wafer is first introduced into the furnace or at the conclusion of the processing as the wafer is being withdrawn from the furnace.

Abstract: An improved gate injected, floating gate memory device is described having improved charge retention and endurance characteristics is described in which the barrier height for the injection of charge (electrons or holes) into the floating gate is reduced. This is accomplished by utilizing a layer of semi-insulating polycrystalline silicon between the control electrode and the insulating layer over the floating gate.

Abstract: A method for protecting electronic circuitry formed on the obverse side of a wafer from flying debris produced either by the mechanical or laser scribing or scoring of the wafer and during separation. The device is provided with a layer of abrasion resistant material on the circuit side of the wafer and the scribing or scoring is done on the obverse side of the wafer. The cracking operation is performed by applying pressure to the wafer in such a manner as to have the reverse side in tension and the obverse or circuit side in compression in order to prevent any debris which may have been cast up during the scribing or scoring operation from contaminating or damaging the circuit side of the wafer while any debris cast up during the breaking operation is thrown away from the obverse or circuit side.

Abstract: The basewidth of a lateral, bipolar transistor is markedly reduced by first forming a layer of polycrystalline silicon over an oxide coated substrate. By utilizing a process for doping the exposed edges of the patterned polysilicon layer, a narrower basewidth dimension is achieved than heretofore possible with photolithographic techniques.

Abstract: A Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) is described wherein a body of semiconductor material is provided with source, drain and channel regions and a gate structure located over the interstitial channel portion of the semiconductor body, between the source and drain regions. A stepped or dual thickness oxide layer, having one portion of minimum thickness formed over only a portion of the channel region and another portion of maximum thickness formed over the remaining portion of the channel region. This stepped oxide layer, together with the gate electrode, forms the gate structure. That portion of the channel region covered by the portion of minimum thickness oxide is separated from the drain region, and the portion of maximum thickness oxide is also located over both a portion of the drain region and that portion of the channel region adjacent the drain region.

Abstract: A Metal-Oxide-Semiconductor-Field Effect Transistor (MOSFET) is described wherein a body of semiconductor material is provided with source, drain and channel regions. A gate structure is provided over the interstitial channel region of the semiconductor body between the drain and source regions, one edge of which is aligned with the source region. The remainder of the channel region, between the other edge of the gate structure and the adjacent edge of the drain region is provided with a drift region of a conductivity type that is opposite to that of the source and drain.

Abstract: A short channel MOS transistor and the method for fabricating same is described wherein the dopant concentrations of the source and drain regions are maintained at different levels of conductivity modifiers. The method described teaches first doping the source region while maintaining the drain region masked and then doping both the source and drain regions.

Abstract: A novel semiconductor configuration is presented utilizing a narrow, gate-like (base) structure formed of, for example, a floating polycrystalline silicon line, that is capable of modulating both the number and type of carriers (electrons or holes) flowing thereunder, between a pair of similarly doped, separated regions. One particular structure described is a four terminal I.sup.2 L configuration where the inverter transistor can function in either the mode of an MOS device or the mode of a bipolar device.

Abstract: A method for fabricating a short channel MOS device is described wherein the conductivity of the gate member is increased by a factor of about 2.5 by counterdoping a P-type doped polycrystalline line with an N-type dopant.

Abstract: A one-piece molded plastic element serves as the sole outer case of an electronic watch. The battery is threaded and screws into one opening in the case. Time setting is accomplished by inserting the ends of a U shaped conductor in other openings in the case. The case is formed with means by which a wrist band may be secured thereto.

Abstract: A complementary-symmetry amplifier is described, wherein a CMOS inverter has its P-channel MOSFET paralleled by the emitter-to-collector path of a simultaneously conductive PNP bipolar transistor and has its N-channel MOSFET paralleled by the emitter-to-collector path of a simultaneously conductive NPN bipolar transistor. The amplifier switches very rapidly due to the high transconductances of the bipolar transistors, while the MOSFET's permit the output terminal of the amplifier to swing over the full range of available supply potential.

Abstract: A generator of recurrent ramp voltages in response to a pulse train. It includes a circuit for ensuring that the output voltage of the generator reaches its maximum value just prior to the occurrence of the next trigger pulse despite such perturbations as a change in the frequency of the pulse train, a change in the value of the circuit supply voltage, or changes in component values.

Abstract: A current mirror amplifier (CMA) with controlled current gain, the current gain being changed, for example, responsive to the output condition of a comparator in which the CMA is used in a differential signal combining circuit. In such a comparator application the switched gain of the CMA imparts hysteresis to the comparator characteristics.

Abstract: A matrix array of semiconductor diodes formed in an epitaxial layer of a semiconductor wafer and being dielectrically isolated from each other by two orthogonal sets of parallel insulating oxide regions, one set extending completely through the epitaxial layer and the other set extending only partially through the epitaxial layer. A preferred method of forming the matrix array is also disclosed.

Abstract: A method of forming dielectrically isolated islands of semiconductor material on which discrete devices may be formed is disclosed. A wafer of semiconductive material is provided with an oxide layer and, by ion implantation, is lightly doped after which, openings are formed in the oxide. The portions of wafer exposed by the openings are then heavily doped and the wafer is then subjected to a high temperature step to drive in the dopants and produce isolated areas.