Patents Represented by Attorney Leffert Jay & Polglaze, P.A.
  • Patent number: 8347893
    Abstract: An assembly for thickening hair has a first adhesive tape, apt to be reversibly adhered on hair, having an adhesive face onto which there are arranged connecting elements of hair extensions of a first plurality of the hair extensions at their respective distal end, and a second adhesive tape, apt to be reversibly adhered on hair, having an adhesive face onto which there are arranged connecting elements of hair extensions of a second plurality of the hair extensions at their respective distal end, the tapes having positioning elements such that the connecting elements of the extensions of said first and second plurality of the hair extensions overlap when the positioning elements are in turn overlapped.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 8, 2013
    Inventor: David Anthony Gold
  • Patent number: 8348185
    Abstract: A shredder feeder has a first receiving post configured to receive a roll of first material, second and third receiving posts respectively configured to receive first and second rolls of second material, and a pair of guideposts that form an outlet of the shredder feeder therebetween. The respective guideposts are positioned to respectively direct the second material from the first and second rolls toward the first material from the roll of first material so that the first material is interposed between the second material from the first roll of second material and the second material from the second roll of second material when the first material and the second materials from the first and second rolls of second material pass concurrently through the outlet.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: January 8, 2013
    Assignee: Identisys, Inc.
    Inventors: Debra R. Ferril, David Roman
  • Patent number: 8345482
    Abstract: Methods for segmented programming, program verify, and memory devices are disclosed. One such method for programming includes biasing memory cells with a programming voltage and program verifying the memory cells with a plurality of ramped voltage signal segments, wherein each ramped voltage signal segment has a different start voltage and a different end voltage than the other ramped voltage signal segments.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 1, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jung-Sheng Hoei
  • Patent number: 8345486
    Abstract: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: January 1, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 8339858
    Abstract: Memory devices and methods of programming memory cells including selecting a voltage to apply to a control gate of the memory cell during programming of a data value of a sense amplifier to the memory cell in response to at least a data value contained in a data latch that is in communication with the sense amplifier.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: December 25, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Patent number: 8335104
    Abstract: A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: December 18, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8327586
    Abstract: A system and methods for controlling operation of hydraulic cylinders includes monitoring position of the cylinders relative to one another, and correction of misalignment of the cylinders should they become misaligned. Further, monitoring can be of a swing-type door operated using the cylinders, which can operate the door at different speeds. Further, as the door creeps open from a closed position or closed from an open position, correction is also made.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: December 11, 2012
    Assignee: Hi-Fold Door Corporation
    Inventors: Richard D Keller, Damian Keller, Daniel Keller, William Bakalich, Steven H. Schultz, Fred W. Sauer, Jaron R. McDaniel
  • Patent number: 8329513
    Abstract: A method of forming a memory array includes forming first and second strings of serially-coupled memory cells respectively on first and second sides of a conductive pillar. Forming the first string of memory cells includes forming a first control gate on the first side of the conductive pillar and interposing a first charge trap between the first side of the conductive pillar and the first control gate. Forming the second string of memory cells comprises forming a second control gate on the second side of the conductive pillar and interposing a second charge trap between the second side of the conductive pillar and the second control gate. The first and second charge traps are electrically isolated from each other, and the first and second control gates are electrically isolated from each other.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 11, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Theodore T. Pekny
  • Patent number: 8325520
    Abstract: A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: December 4, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Patent number: 8327224
    Abstract: Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: December 4, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Troy Larsen, Martin Culley, Troy Manning
  • Patent number: 8321713
    Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: November 27, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Dean Nobunaga
  • Patent number: 8316165
    Abstract: A device has a controller and a function module configured to be in communication with the controller as a result of the controller receiving a pass-through vendor specific command. In some embodiments, the controller is configured to receive the pass-through vendor specific command from an application software module of a host through an interface that is configured in accordance with a standard that does not allow communication to occur between the controller and the function module.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: November 20, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Anson Ba Phan, Jerrold Allen Beckmann
  • Patent number: 8316209
    Abstract: A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: November 20, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Wanmo Wong
  • Patent number: 8307152
    Abstract: In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: November 6, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei
  • Patent number: 8304309
    Abstract: Methods of forming memory and memory devices are disclosed, such as a memory device having a memory cell with a floating gate formed from a first conductor, a control gate formed from a second conductor, and a dielectric interposed between the floating gate and the control gate. For example, a select gate may be coupled in series with the memory cell and has a first control gate portion formed from the first conductor and a second control gate portion formed from a third conductor. A contact may be formed from the third conductor and coupled in series with the select gate. Other methods and devices are also disclosed.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 6, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Andrew Bicksler
  • Patent number: 8296545
    Abstract: In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated therewith and all of the blocks of the nonvolatile memory having collectively a capacity status associated therewith and a display for showing the capacity status even when no power is being applied to the display.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Petro Estakhri, Martin Ragnar Furuhjelm, Ngon Le, Jerrold Allen Beckmann, Neal Anthony Galbo, Steffen Markus Hellmold, Jarreth Romero Solomon
  • Patent number: 8296692
    Abstract: A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Patent number: 8295088
    Abstract: A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell that is coupled to a reference bit line. A voltage is precharged onto a bit line to be read and an associated reference bit line. The bit line is then coupled to a NAND string and selected memory cell while the reference bit line is coupled to a reference NAND string and selected reference memory cell. The relative voltage level of the bit line and reference bit line are then set by the relative currents flowing through the coupled NAND string and reference NAND string, and the voltage differential read by a coupled voltage sense amplifier.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Daniel Doyle
  • Patent number: 8295098
    Abstract: Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Dean Nobunaga, William Kammerer, Uday Chandrasekhar
  • Patent number: 8295109
    Abstract: Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, William H. Radke, Dzung H. Nguyen