Abstract: Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.

Abstract: Systems having a host computer system, a memory device coupled to the host computer system, and identification circuitry. The identification circuitry is configured to identify an operating mode of the host computer system from comparing applied signals to sensed signals.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.

Abstract: A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.

Abstract: A nipple of a check has a first portion that is selectively positionable within a housing of the check valve. A second portion of the nipple extends from the housing when the first portion of the nipple is selectively positioned within the housing. The check valve is configured to allow fluid flow through the check valve in either a first direction or a second direction when the first portion of the nipple is selectively positioned within the housing. The check valve is configured to prevent fluid flow through the check valve in the first direction when the first portion of the nipple is removed from the housing.

Abstract: Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over the trench, and, for certain embodiments, this control gate may extend into the trench. The charge carrier trapping sites may be discrete formations on a sidewall of a trench, a continuous layer extending from one sidewall to the other, or plugs extending between sidewalls.

Abstract: Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.

Abstract: Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data.

Abstract: A write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. A read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.

Abstract: Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized to tighten the distribution of threshold voltages for a given bit pattern by compensating for anticipated threshold voltage shift due to capacitive coupling, which can facilitate more discernable Vt ranges, and thus a higher number of bits of data per memory cell. Tightening the distribution of threshold voltages can further facilitate wider margins between Vt ranges, and thus an increased reliability in reading the correct data value of a memory cell.

Abstract: A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to substantially concurrently substantially fill the first trench and partially fill the second trench. The layer of material is removed substantially concurrently from the first and second trenches to expose substantially all of the dielectric liner within the second trench and to form a plug of the material in the one or more first trenches. A second layer of dielectric material is formed substantially concurrently on the plug in the first trench and on the exposed portion of the dielectric liner in the second trench. The second layer of dielectric material substantially fills a portion of the first trench above the plug and the second trench.

Abstract: Memory devices, memory systems, discharge circuits, and methods for discharging a capacitance are disclosed. In one such memory device, a discharge circuit is coupled to memory support circuitry. When a supply voltage decreases to be less than or equal to a trip voltage, the discharge circuit discharges a voltage from a capacitance of the memory support circuitry.

Abstract: In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.

Abstract: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.

Abstract: A container for an electronic device has pivotally coupled first and second portions. The first portion is configured to house the electronic device and has an opening for receiving the electronic device and for displaying the electronic device when the container is configured in a first configuration. The second portion is configured to act as a mount for mounting the container on a surface when the container is configured in the first configuration and the first portion is displaying the electronic device. The second portion is further configured to cover the opening in the first portion, and thus the electronic device, when the container is configured in a second configuration.

Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.

Abstract: Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC time constant of the memory cell signal line.

Abstract: Methods for programming memory devices, a memory device, and memory systems are provided. According to at least one such method, bit lines a memory segment are read at substantially the same time by coupling a selected memory segment, and at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines. Other methods, devices, and systems are also provided.

Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.