Abstract: An adaptive prediction filter which provides recursive calculation of prediction coefficients from sampled values of segments of a sampled audio signal. In order to obtain improved computation accuracy the coefficients are in block floating point format, and are recursively calculated from reflection coefficients. Upon calculation of a kth reflection coefficient the k-1 previously computed prediction coefficients are recomputed again based thereon. In the event that results in an overflow of the number of bits in the mantissa of a prediction coefficient which is being calculated, the block floating point format is adapted by increasing the common exponent of the block. That conventionally required recalculation of all previously recalculated coefficients.

Abstract: A data transmission system wherein data to be transmitted is supplied to an encoding device (5) which comprises a data analysis circuit (35) for producing a parity code and an output circuit (32) for assigning the parity code to the input data so as to convert it into protected data for transmission. The data analysis circuit includes: (i) a serial-to-parallel converter (30) for converting the input data into "n" parallel data streams, the bits in each stream being at instants which are multiples of n.times.T, where T is the bit period of the input data; (ii) "n" cascade combinations of delay elements, each cascade delaying one of the "n" parallel-converted data streams by time periods which are multiples of n.times.T, each cascade having tapping points following certain ones of the delay elements therein; and (iii) combining circuits (GR1, GR2, OE) having inputs connected to tapping points of each of the cascade combinations and which derive the parity code.

Abstract: The system according to the invention forms part of a modem that is constituted, on the one hand, by a signal processor (60) to which is connected a read-only memory (65) and, on the other hand, by supplementary circuits such as a digital/analog converter (20) for supplying the transmission signals to the telephone line (9) and an analog/digital converter (30) for digitizing the analog signals coming from the telephone line (9). The conversions are performed at rates determined by clocks (20) and (30). Task series (CH1, CH2) bearing different degrees of priority are associated to these signals. The invention resolves the priority conflicts by closely examining the clock signals and by executing first the tasks that have the highest priority (TR1 for series CH1 and REC1 for series CH2) if the close examination of the signals proves them to have priority and then, when no priority is detected, the other tasks (TR2, GES for series CH1 and REC2 and REC3 for series CH2).

Abstract: An amplifier, particularly a CMOS amplifier has a differential input which is fed to six differential pairs. The outputs of the first and third differential pair are combined and fed to inputs of a summing network, while the outputs of the fourth and fifth are combined and fed to inputs of the summing network. The second and sixth differential pairs are arranged to cancel the tail currents of the fifth and third pairs, respectively, when all of the devices are in their active state. Thus, regardless of the common mode input level with respect to the supply rails the output current is provided by four devices giving a constant g.sub.m and slew rate.

Abstract: An in-the-ear hearing aid has a collar which can form a flexible seal in the bony part of the ear canal so as to reduce the occlusion effect. The collar comprises a tubular portion which is engageable against the wall of the ear canal, a fixing portion and a curved sealing portion. Owing to the use of this collar it is not necessary to make a mold of the bony part of the ear canal. This collar enables the hearing aid to be constructed in a manner such that it can be inserted so deep into the ear.

Abstract: A level-shifting circuit (LS.sub.A) including a series arrangement of a load resistor (R.sub.A), a main current path of an input transistor and a bipolar series transistor (T3.sub.A) arranged as a current source and having a parasitic transistor with a small current gain factor, which is obtained, for example, by wholly surrounding the comparatively weakly doped collector region with a comparatively heavily doped material of the same conductivity type as the collector region. When the input transistor (T1.sub.A) is not conductive a large amount of charge accumulates in the series transistor (T3.sub.A), which is then in saturation. When the input transistor (T1.sub.A) is turned on the accumulated charge causes an overshoot in the current (I.sub.A) through the level-shifter which overshoot compensates for the slow response as a result of the parasitic capacitance (PC.sub.A) at the node (N.sub.A).

Abstract: An audio signal digital transmission system wherein the signal is sampled and successive segments each of N samples are digitally encoded. Encoding has heretofore been effected by vector quantization, whereby a memory stores a book of a large number of codewords corresponding to possible segments of successive signal samples, and the best matching stored segment is determined by calculation. The present invention bases encoding on comparison of the envelope of a signal segment with a limited number of reference envelopes. The best matching reference envelope is selected, and an identifying codeword therefore is transmitted along with related parameters. A receiver reproduces the signal from the reference envelope and the related parameters. Since identified envelopes of the signal segments are less variable and simpler to evaluate than the signal samples in the segments, a considerable reduction of memory capacity and calculation complexity is achieved.

Abstract: A full-flash N-bit analog-to-digital converter with Gray-code digital output (V.sub.out) comprises only N current sources (CS.sub.1, CS.sub.2, CS.sub.3) to power the 2.sup.N -1 differential amplifiers connected to a voltage reference ladder RL and only N latches (L.sub.1, L.sub.2, L.sub.3) which directly furnish an N-bit Gray code at their outputs (LO). For this purpose the differential amplifiers are grouped and stacked in a particular manner and the output signals of the individual differential amplifiers in a group are cross-coupled to the inputs (LI.sub.1, LI.sub.2) of the latch associated with the group.

Abstract: A telecommunication exchange is described for switching through telecommunication links, which is controlled by a processor system. The processor system comprises a plurality of parallel-arranged modules which have each a processor. In an operating mode of the processor system the processors operate mutually synchronously. The processor system utilizes a fault-tolerant code. As a result, the entire processor system continues to operate even if faults occur in certain modules. The processor system is further arranged for operating in a software load mode. In this mode the processor system is subdivided into two groups of modules. The processors of the modules of each group operate mutually synchronously. The modules of each group use the code section generated by the modules of that particular group to operate.

Abstract: A knee circuit in which the hue on the output side does not differ from the hue on the input side. The knee circuit includes a virtual luminance signal generator for generating a virtual luminance signal Y based on at least one input color signal Rin, Gin and Bin, a virtual correction value generator for monitoring whether the virtual luminance signal Y is equal to or greater than a knee point NP and for generating a virtual correction value Yk by performing a knee correction with respect to the virtual luminance signal Y when it is equal to or greater than the knee point NP. A proportional value generator generates a proportional value Kk showing a ratio of the virtual correction value Yk to the virtual luminance signal Y by dividing the virtual correction value Yk by the virtual luminance signal Y.

Abstract: An ink jet recording device includes an ink jet recording head comprising at least one pressure chamber communicating with an ink reservoir via an ink supply channel and a nozzle plate comprising at least one nozzle opening for emitting droplets of ink, the nozzle plate forms a wall of the pressure chamber. The recording head further comprises a piezoelectric actuator element having an active direction and comprising at least one layer of piezoelectric material and at least two electrode layers which are arranged such that the dimension of the actuator element in the active direction is varied upon application of an electric voltage between terminals that are electrically connected to the electrode layers. The actuator element is arranged in cooperative relationship with the pressure chamber so that the pressure chamber changes its volume when the dimension of the actuator element in the active direction is varied.

Abstract: A synchronous data transmission system includes modems and data packet switches having interfaces in compliance with CCIT recommendation V24. However, verification of correct operation of the modems is preferably carried out by the system control center by transmission of control instructions which are asynchronous, such as Hayes instructions. To make this possible without requiring additional circuitry, the modems are of the bi-mode type, having a synchronous and an asynchronous mode, and during control of a modem the interface circuits at the relevant packet switch are set to the asynchronous mode. The modem detects that condition of the packet switch interface circuit, and sets its own interface circuits to correspond therewith. The interface circuits are then reset to the synchronous mode after completion of the control operation.

Abstract: A current memory has an input (1) which is connected via a switch (S1) to inputs of a coarse memory cell (CM) and a fine memory cell (FM). On a phase .phi.1 of a clock signal the switch (S1) closes. During a first part .phi.1a of the clock .phi.1 of the coarse memory cell samples the input current and the outputs the sampled current thereafter. During a second part .phi.1b of the clock .phi.1 the fine memory cells senses and stores the difference between the input current and the output current of the coarse memory (CM). An output switch (S5) closes on phase .phi.2 of the clock, thereby passing the combined outputs of the coarse and fine memories to an output (2). A resistor r.sub.s is provided between the common nodes of the coarse and fine memories, having a resistance equal to the "on" resistance of the output switch (S5).

Abstract: A current comparator arrangement has first and second inputs (100, 103), an output (105), and cross-coupled transistors (MP1, MP2) which form a latching circuit. The arrangement also includes current stores (MP3, MP4), the input currents to be compared being fed to the current stores in a selected forward differential order for storage therein during a first portion of a clock period in which the cross-coupled latching circuit is reset. During a second portion of the clock period the input current connections are reversed, thereby reversing their differential order, and the reverse order currents are supplied together with the stored forward order currents to the latching circuit. This cancels common mode and offset currents so that they do not affect the comparison of the input currents.

Abstract: A circuit arrangement for supplying a constant current which is stabilized against temperature variations. The constant current is produced by a current source which is controlled by a control stage in which a first control current is supplied to each of a first and a second resistor, at least one of which is trimmable. The first control current is controlled so that the difference between the voltages produced thereby across the first and second resistors is in a first predetermined ratio to the constant voltage produced by a reference voltage source. The current source is controlled by the control stage so that the constant current produced thereby is in a second predetermined ratio to the first control currents.

Abstract: A laser power supply control circuit may, when the power supply is initially turned on, temporarily permit an excessive supply voltage which may damage the laser. To prevent that, but without restricting the operating range or speed of response of the control circuit, the invention provides a sensing circuit for deriving a sensor signal indicative of a change in the loop gain of the control circuit when it departs from its normal operating mode. The sensor signal is used to prevent the power supply control signal from increasing excessively after a temporary reduction in supply voltage, but permits the control signal to operate substantially immediately when the supply voltage returns to its normal operating range.

Abstract: A circuit arrangement for optionally applying an antenna signal to a receiver section of a video recorder or to a television receiver connected to the video recorder, by a switching device enabling the antenna signal to be applied only to the receiver section of the video recorder and to be passed from the video recorder to the television receiver in the blocked state of said switching device, and enabling the antenna signal to be applied directly to the television receiver in the conducting state of the switching device. A loop-through of the antenna signal to the television receiver will then also be possible when the video recorder does not convey any current.

Abstract: An information retrieval system in which information is stored in digital form in a serial access device such as a digital VCR, the information being organized as a library of successive albums, each album having successive tracks of individually identifiable items of information, such as audio performances, subjects or events. A random access device, such as a compact disc player or magnetic hard disc drive, has stored therein a portion of a preselected track of each album and a brief introductory portion of each of the remaining tracks in each album. Both devices are coupled to a common data bus and are controlled by a programmable processor so that during search intervals of the serial access device to access a selected album or track read-out thereof is initiated by the random access device. When the serial access device is ready to access selected track or album, read-out is switched over thereto.

Abstract: A device compensated for an undesired capacitance includes a first and a second node between which nodes the undesired capacitance is present. A diode driven in breakthrough is coupled between the first and the second node. As a diode driven in breakthrough exhibits the characteristics of a negative capacitance, a compensation of the undesired capacitance is achieved.

Abstract: In a transmitter in a coherence multiplexed transmission system the output signal of a laser is directly applied to a channel and indirectly via a plurality of cascaded circuits of delay elements and modulators. The modulators vary a component of the autocorrelation function of the output signal of the transmitter as a function of an associated modulation signal (m.sub.1, m.sub.2, m.sub.3). In the receiver the autocorrelation functions values of the channel output signal for delays (D.sub.1, D.sub.2, D.sub.3) are determined in the demodulators. These autocorrelation function values from the modulated signal (m.sub.1 ', m.sub.2 ', m.sub.3 '). To reduce the number of periodic components of the autocorrelation function of the signal source, and hence enhance the possible transmission capacity, the transmitter comprises a decorrelation modulator for modulating the signal source with pulses generated by a pulse generator.