Patents Represented by Attorney Lindsay G. McGuinness
  • Patent number: 7916918
    Abstract: A method includes acquiring first imaging information of a region of interest, said first imaging information providing data correlated to three spatial dimensions of a reference frame including said region of interest; acquiring second projection imaging information of said region of interest, said second imaging information providing data correlated to said reference frame but is lacking information concerning at least one spatial dimension; and processing said first and second imaging information such that said first imaging information is registered with said second imaging information.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: March 29, 2011
    Assignee: Hologic, Inc.
    Inventors: Jasjit S. Suri, Roman Janer, Yujun Guo, Idris A. Elbakri
  • Patent number: 7872681
    Abstract: A method of implementing high-performance color filter mosaic arrays (CFA) using luminance pixels. The introduction of luminance pixels greatly improves the accuracy of the image acquisition process for a given pixel and image sensor size.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: January 18, 2011
    Assignee: RJS Technology, Inc.
    Inventor: Sorin Davidovici
  • Patent number: 7800669
    Abstract: A solid-state pixel structure or pixel array includes integrated exposure control provided within the pixel structure and/or pixel array. Including exposure control within the pixel structure and/or array allows optimal exposure to be achieved in real time. Optimal exposure is achieved by measuring the response of pixel structures to received electromagnetic radiation, and using the response information, in conjunction with knowledge regarding the pixel structure capabilities and photometric thresholds, to determine when the pixel structure is operating optimally. Tight control of the exposure of the pixel structure to the electromagnetic radiation allows the pixel structure to operate optimally in order to provide an optimal captured image.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: September 21, 2010
    Assignee: R.J.S. Technology, Inc.
    Inventor: Sorin Davidovici
  • Patent number: 7786422
    Abstract: A high dynamic range sensitive sensor element or array is provided which uses phase domain integration techniques to accurately capture high and low intensity images. The sensor element of the present invention is not limited by dynamic range characteristics exhibited by prior art solid-state pixel structures and is thus capable of capturing a full spectrum of electromagnetic radiation to provide a high quality output image.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: August 31, 2010
    Assignee: RJS Technology, Inc.
    Inventor: Sorin Davidovici
  • Patent number: 7782369
    Abstract: A high dynamic range sensitive sensor element or array is provided which uses phase domain integration techniques to accurately capture high and low intensity images. The sensor element of the present invention is not limited by dynamic range characteristics exhibited by prior art solid-state pixel structures and is thus capable of capturing a full range of electromagnetic radiation to provide a high quality output image.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: August 24, 2010
    Assignee: RJS Technology, Inc.
    Inventor: Sorin Davidovici
  • Patent number: 5751554
    Abstract: An integrated circuit handling, packaging and testing apparatus in the form of a testable chip carrier comprising a rigid substrate onto which a chip may be bonded, and which provides a high density interconnect pattern orthogonally aligned to the chip bond pads for wire bonding thereto. The interconnect also provides external bonding points patterned for similar orthogonal alignment to the external device to which the chip is to be connected, and the dimensions of the carrier are substantially smaller than an equivalent standard or custom package type. A hermetic or non-hermetic seal lidding operation may be carried out on the chip and carrier. The carrier also provides a detachable test perimeter allowing full-functional testing and burn-in of the attached wire-bonded chip prior to placement on a printed circuit board or multi-chip module.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: May 12, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Simon Mark Williams, Michael Lawrence McGeary
  • Patent number: 5745259
    Abstract: An apparatus for dithering an input image to produce an output array for representation on an output device is described. The apparatus includes an input device to store input image pixels having a first plurality of chrominance or luminance levels; a dithering system including a dither template including an M by N matrix of integer threshold values, the uniform distribution of threshold values throughout the dither template possessing homogeneous attributes. The apparatus further includes a normalizer unit for normalizing the threshold values of the dither template for storage in a dither matrix according to the first plurality of chrominance or luminance levels of the input image pixels and a second plurality of chrominance or luminance levels of the output array and a summation unit to add the input image pixel chrominance or luminance values to the normalized threshold values of the dither matrix.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: April 28, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Robert Alan Ulichney
  • Patent number: 5675763
    Abstract: A cache memory system and method for selectively removing stale "aliased" entries, which arise when portions of several address spaces are mapped into a single region of real memory, from a virtually addressed cache, are described. The cache memory system includes a central processor unit (CPU) and a first-level cache on an integrated circuit chip. The CPU receives tag and data information from the first level cache via virtual address lines and data lines respectively. An off-chip second level cache is additionally coupled to provide data to the data lines. The CPU is coupled to a translation lookaside buffer (TLB) via the virtual address lines, while the second level cache is coupled to the TLB via physical address lines. The first and second level caches each comprise a plurality of entries. Each of the entries includes a status bit, indicating possible membership in a class of entries that might require flushing.
    Type: Grant
    Filed: August 4, 1995
    Date of Patent: October 7, 1997
    Assignee: Digital Equipment Corporation
    Inventor: Jeffrey Clifford Mogul
  • Patent number: 5648909
    Abstract: In a method for improving a circuit having a logically false path through static analysis of a software model, a computer receives information describing the false path, determines a true path alternate to the false path, and analyses the circuit model with respect to the true path.
    Type: Grant
    Filed: June 12, 1995
    Date of Patent: July 15, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Larry L. Biro, Joel J. Grodstein, Jeng-Wei Pan, Nicholas L. Rethman
  • Patent number: 5634014
    Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.
    Type: Grant
    Filed: July 12, 1995
    Date of Patent: May 27, 1997
    Assignee: Digital Equipment Corporation
    Inventors: William B. Gist, Joseph P. Coyle
  • Patent number: 5630055
    Abstract: A computer system includes a central processing unit which further includes an execution unit and two levels of data cache and an error checking and correcting unit. During error-free operation, external cache fill data is supplied directly to the execution unit while a copy of the data is checked by the error checking and correcting unit. In response to detection of an error by the error checking and correcting unit, the use of the fill data by the execution unit is aborted. Furthermore, the data path for fill data is dynamically reconfigured to force remaining pending fill data to pass through the error checking and correcting unit prior to reaching the execution unit or either of the caches. Once all pending fill data has been processed, the data path is reconfigured back to its error-free mode of operation such that fill data is transmitted directly to the execution unit while a copy of the data is checked by the error checking an correcting unit.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: May 13, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Peter J. Bannon, Ruben W. Castelino, Chandrasekhara Somanathan
  • Patent number: 5629950
    Abstract: The present invention is directed to a method of managing a cache upon detection of an address TAG parity error, The cache includes a plurality of entries for storage of data, with each entry having a corresponding address TAG entry. The method includes the steps of performing a TAG parity check for each access to the cache, and upon detection of a parity error in an address TAG, disabling allocation of TAG entries for storage of new address TAGs. A signal indicating the TAG parity error is transmitted to an error correction mechanism.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: May 13, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Nitin D. Godiwala, Kurt M. Thaller, Jeffrey A. Metzger, Barry A. Maskas
  • Patent number: 5617283
    Abstract: An ESD protection device is provided which includes a self referencing modulation circuit for controlling its operation. The modulation circuit includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of series connected inverters powered by the signal pad voltage in an alternate embodiment. The inverter chain is coupled to the ESD clamp. The modulation circuit requires no reference supply voltage to operate. The ESD protection circuit shunts currents associated with ESD events away from ICs as well as clamping I/O pad voltages to acceptable levels during an ESD event.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: April 1, 1997
    Assignee: Digital Equipment Corporation
    Inventors: David B. Krakauer, Kaizad Mistry, Steven Butler, Hamid Partovi
  • Patent number: 5615167
    Abstract: A computer system comprising one or more processor modules. Each processor module comprising a central processing unit comprising a storage element disposed in the central processing unit dedicated for storing a semaphore address lock value and a semaphore lock flag value, a cache memory system for storing data and instruction values used by the central processing unit, a system bus interface for communicating with other processor modules over a system bus, a memory system implemented as a common system resource available to the processor modules for storing data and instructions, an IO system implemented as a common system resource available to the plurality of processor modules for each to communicate with data input devices and data output devices, and a system bus connecting the processor module to the memory system and to the IO system.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: March 25, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Anil K. Jain, John H. Edmondson, Peter J. Bannon
  • Patent number: 5602941
    Abstract: This disclosure relates to an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, which has a greater or equal number of input levels. Generally, neither the number of input nor output levels need to be a power of two. The present invention is implemented in a number of different embodiments. These embodiments generally rely upon an image processor which, depending on the particular implementation, includes memory devices and an adder, a comparator, or a bit shifter. Additional embodiments use an image adjustment system or an image modification system to refine the raw input levels of the input device, in order to create an improved output image. Also, the particular embodiments of the image processors can be used in connection with imaging systems having bi-tonal, monochromatic, or color input and output devices.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: February 11, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Patrick D. Charles, Robert S. McNamara, Robert A. Ulichney
  • Patent number: 5596715
    Abstract: An apparatus for providing data to an I/O bus at the maximum I/O bus bandwidth comprises an exerciser unit coupled to the I/O device. The exerciser unit includes DMA circuitry for providing a constant stream of transactions to the I/O bus. Each transaction provides a plurality of data quadwords to the I/O bus which are parity protected. The exerciser unit includes a memory device for storing data to be provided for each transaction, and a parity circuit for calculating and providing parity for the data stored in the memory. The exerciser unit further includes a data generation device for providing both data having predictable parity and the parity to the bus for each bus cycle while bypassing the parity generation logic to provide data at maximum bandwidth. The data generation device provides a sequence of different data bytes using a modified Gray-code algorithm, which facilitates parity generation for each byte in the sequence of bytes.
    Type: Grant
    Filed: August 4, 1995
    Date of Patent: January 21, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Philippe Klein, David W. Maruska, Kevin W. Ludlam
  • Patent number: 5594741
    Abstract: A method of testing an integrated circuit design includes the steps of providing a logical model of an integrated circuit, having a plurality of data ports, providing at least two simulators, the first simulator coupled to a first data port of the integrated circuit model, and the second simulator coupled to a second different data ports of said integrated circuit model. The further includes the steps of providing an instruction stream to the first and second simulators, the instruction stream including at least two instruction threads corresponding to the at least two simulators, the simulators providing signals to the data ports in accordance with instructions provided from each of the instruction threads. In addition, the method further includes the step of delaying the first simulator from processing its corresponding instruction thread until dependencies between instruction threads have been satisfied.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: January 14, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Paul M. Kinzelman, Nicholas A. Warchol
  • Patent number: 5587964
    Abstract: A page mode/nibble mode dynamic random access memory (DRAM) comprising row and column decoders, the column decoder further comprising a column address buffer and a column address buffer counter. The page mode/nibble mode DRAM also comprises a buffer controller means adapted to receive a write enable signal and to determine whether the DRAM should be placed in a page mode or a nibble mode to facilitate the particular memory access requested by a memory controller. An asserted write enable signal, may indicate, for example, a write operation, thereby calling for the page mode/nibble mode DRAM to move into a page mode to effectuate the write operation. The page mode/nibble mode DRAM also utilizes the write enable signal in the conventional manner, to indicate the initiation of a particular type of memory access, namely a write operation or a read operation.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: December 24, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Mitchell N. Rosich, William L. Lippitt
  • Patent number: 5570459
    Abstract: An output device is enabled to obtain character descriptions for use in raster scanning characters which belong to a common character font. Character descriptions are stored in an external device which is linked to the output device by a communication channel. Character codes are received at the output device which identify characters to be outputted. A raster image of the characters to be outputted is set up. In the course of setting up the raster image, information corresponding to the character codes is sent from the output device to the external device via the communication channel. In response to the character codes sent from the printer to the external device, corresponding character descriptions are sent from the external device to the output device via the communication channel.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: October 29, 1996
    Assignee: Digital Equipment Corporation
    Inventor: Chi S. Kam
  • Patent number: 5559953
    Abstract: An apparatus and method for storing pixel data in a video memory having a plurality of slices increases the performance of line drawing by ensuring that for a given pixel, neighboring pixels in neighboring scan lines are stored in separate slices of video memory. One embodiment of the invention includes the step of appending a number of offset bits to the end of each scan line, where the number of offset bits is less than the total number of bits contained in the plurality of slices. Another embodiment of the invention rearranges the pixels of every other scan line. Another embodiment adds an offset number of pixels which is equal to the number of pixels per slice times the number of slices, then alternates ordered pixels with rearranged pixels throughout successive scan lines. Performance is further increased by providing a plurality of memory controllers corresponding to the plurality of slices of memory which may operate asynchronously to interleave memory access commands.
    Type: Grant
    Filed: July 1, 1994
    Date of Patent: September 24, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Larry D. Seiler, Robert S. McNamara, Christopher C. Gianos, Joel J. McCormack