Patents Represented by Attorney, Agent or Law Firm Loeb & Loeb LLP
  • Patent number: 6017373
    Abstract: An artificial firelog which contain 2% to about 6%.sub.w coriander seed added to create a crackling sound that mimics the sounds produced during the burning of natural logs. The random crackling sound continues for approximately the same time period as observed with the burning of natural wood firelogs and has an amplitude and frequency of crackling sound that mimics burning natural wood logs.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: January 25, 2000
    Assignee: Duraflame, Inc.
    Inventor: Gary Frisch
  • Patent number: 6016265
    Abstract: A semiconductor IC apparatus including a fuse-latch unit. The fuse-latch unit comprises many fuses and latch output circuits. The fuses and the latch output circuits are arranged at pitches as short as possible, leaving virtually no dead spaces between them. The fuse-latch unit is therefore short in the direction the fuses and latch output circuits are arranged, thus occupying only a small area. The latch output circuits are arranged in two parallel columns. The fuses are arranged in one column extending between the two columns of latch output circuits. The fuses are connected, alternately to the latch output circuits of the first column and those of the second column.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: January 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Munehiro Yoshida, Ryouji Kotani
  • Patent number: 6015101
    Abstract: A gas burner system which can be used in a conveyor-type oven has a burner tube (4) extending across the conveyor. Gas is burnt through a slot (8) along the tube to give a ribbon flame. The tube (4) is divided into separate compartments (15-19) which connect with different lengths of the slot (8). Combustible gas is fed under independent control to the different compartments (15-19), and the slot lengths are adjustable. The slot lengths consist of short edge-region slots and multiple, longer central region slots.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: January 18, 2000
    Assignee: APV UK Ltd.
    Inventors: Mark Williamson, Derek Davies
  • Patent number: 6014443
    Abstract: Cryptographic key data and data subjected to an operation by use of the cryptographic key data are previously stored in a memory cell array. A memory cell in which the cryptographic key data is stored is accessed and latched and the cryptographic key data is latched in a latch circuit before read out data from the memory cell array. After this, the latched data and data output from a sense amplifier are subjected to an operation by an arithmetical circuit to decode the data and the result of the operation is output as readout data.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: January 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Mochizuki, Yuuichi Tatsumi
  • Patent number: 6014335
    Abstract: It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, spare DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: January 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Patent number: 6014494
    Abstract: In tracing a tape with a signal recording head to form tracks having digital data recorded thereon, a plurality of tracks provide each of blocks, and a usual playback data area NA and trick playback areas TH and TL are arranged on each of the tracks included in each block. The trick playback areas are enlarged to provide increment areas TA with a decrease in the bit rate of usual playback data. In recording image data as to a plurality of programs on a tape conjointly, signal recording tracks are formed on the tape, and a usual playback data area and a trick playback data area are formed on each of the tracks or on one track per plurality of tracks, as arranged longitudinally of the track, whereby the image data as to programs A to D is conjointly recorded on the same tape.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: January 11, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigekazu Minechika, Kazuyuki Okamoto, Osami Sunagawa, Masahiko Nishikawa, Takashi Ohnaka, Hirotsugu Murashima, Tatsuo Tanaka
  • Patent number: 6010923
    Abstract: There is provided a semiconductor device in which a semiconductor layer and a gate electrode are formed with a gate insulating layer between then and in which a region of the semiconductor layer opposite to the gate electrode is used as a channel region. On the semiconductor layer, an insulating protection film and an amorphous semiconductor layer are successively formed. The protection film covers at least the channel region of the amorphous semiconductor layer, and annealing is applied to the amorphous semiconductor layer, thereby converting the amorphous semiconductor layer into the polycrystal semiconductor layer. A portion to be the channel region of the amorphous semiconductor layer is covered by the protection film. Therefore, even when exposed to the atmosphere due to annealing, surface contamination can be prevented and a semiconductor device having satisfactory characteristics can be obtained. A thickness d of the protection film is set to be nearly ".lambda./4n" for a wavelength .lambda.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: January 4, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Yushi Jinno
  • Patent number: 6011690
    Abstract: A PC card comprising a housing including top and bottom cover panels encloses at least one heat-generating circuit component, typically an IC device or package. A heat spreading element, which may be in the form of a copper sheet, is disposed in conduction heat transfer relationship with the at least one circuit component and at least one of the housing covers, the heat spreading element being adapted to receive heat from the at least one circuit component, to spread the heat uniformly and to transfer it to the at least one housing cover panel. From there, the heat is dissipated into the surrounding environment.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: January 4, 2000
    Assignee: Xircom, Inc.
    Inventors: James G. Hughes, John N. Otey, Son Nam Doan
  • Patent number: 6010947
    Abstract: An end portion of a trench isolating region has a shape of steps so that a residual gate material can be easily removed and it is possible to prevent from conducting between gates. An oxide film 2, a first stopper 3 and a second stopper 4 are formed on a semiconductor substrate 1 (FIG. 1A). The materials of the first and second stoppers may be selected from materials having different oxidation rates, materials having different isotropic etching rates and the combinations thereof. Then, a resist is formed by patterning, and then, the anisotropic etching of the second stopper 4 of a silicon nitride layer, the first stopper 3 of a polycrystal silicon, the oxide film 2 and the semiconductor substance 1 is carried out (FIG. 1B). After peeling off the resist 7, oxidation is carried out by tens nm to form an oxide film 5 (FIG. 1C). At this time, since the first stopper 3 is made of a material which is easily oxidized, the oxide film 5 grows in a lateral direction to be formed therein. Then, a SiO.sub.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: January 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Kondo
  • Patent number: 6011713
    Abstract: A semiconductor memory includes a memory cell including inverters (IN1, IN2), control transistors (T3, T4) that control the potential of a ground side terminal (N3) connected to the memory cell, and transfer transistors T1 and T2 that control transfer of data from bit lines (BL, /BL) to the memory cell. In writing data, the control transistors raise the potential of the ground side terminal (N3) to be higher than the ground potential by a predetermined potential. After the transfer transistors transfer data having a potential difference smaller than a potential difference between the power supply potential and the ground potential from the bit lines (BL, /BL) to the memory cell, and cause the memory cell to hold the data, the potential of the ground side terminal (N3) is decreased to the ground potential to write data.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: January 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumiyuki Yamane, Tadahiro Kuroda, Toshinari Takayanagi, Masataka Matsui, Yasuo Unekawa, Tetsu Nagamatsu
  • Patent number: 6011312
    Abstract: A semiconductor package is provided that includes a semiconductor chip that is mounted on a mount board with metal bumps interposed therebetween so as to create a gap. A structure is provided in the gap for limiting the flow of a resin, which is deposited along side the semiconductor chip, around the peripheral portion of the semiconductor chip. The structure increases the resistance to the flow of the resin in the peripheral portion of the semiconductor chip. Therefore, the rate at which the resin flows in the peripheral portion of the semiconductor chip is made lower than the rate at which the resin flows near the central portion of semiconductor chip. Accordingly, the formation of a resin-less void in the gap is suppressed so that the grade and quality of the semiconductor device is improved. In one embodiment, the structure in the gap includes projections provided on a portion of the mount board that corresponds to the peripheral portion of the semiconductor chip.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: January 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahito Nakazawa, Yumiko Ohshima
  • Patent number: 6010336
    Abstract: A living body-supporting member having a surface layer with multiple pores regularly arranged therein, in which the porous portions constituting the living body-supporting member are made of ceramics giving no harm to a human body. And a method to perforate multiple pores in a green sheet made of the ceramics, to laminate the green sheets so that pores communicate with each other, and to fire it. The living body-supporting member is coupled with the bone, and there is no risk that it may drop from the supporting portion. Even if the substrate is composed of ceramics, the substrate and the surface layer can be integrally coupled with each other, thereby there is no risk that both of them are separated. Furthermore, according to the above method, the pore shapes of the porous body can be preliminarily designed so that pores communicate with each other while being displaced for every certain depth, and it can be accurately controlled in the production thereof.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: January 4, 2000
    Assignee: Kyocera Corporation
    Inventors: Toshihiko Shimotoso, Akira Terui, Hiroyuki Kitano
  • Patent number: 6007677
    Abstract: Apparatus for continuously processing wood product formed from random lengths of wood strips assembled in face-to-face relationship with heat curable adhesive applied to adjacent contacting faces of the strips includes a pair of opposed, parallel, linear arrays of electrically insulative blocks, the linear arrays of blocks having inner, confronting faces spaced apart transversely to define an elongated, longitudinally extending press zone into which the product is adapted to be fed. A drive motor is coupled to each linear block array for moving the arrays in the same direction in unison to thereby advance the stock in the press zone. An adhesive RF curing zone substantially coextensive with the press zone is defined by the inner confronting faces of the block arrays and first and second elongated, parallel RF electrodes disposed between the confronting inner faces of the block arrays.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: December 28, 1999
    Assignee: G. W. Manufacturing Co., Inc.
    Inventor: Thomas P. Skuse
  • Patent number: 6006619
    Abstract: An engine or like apparatus includes a linear-to-rotational motion converting mechanism which emulates an elliptic trammel or ellipsogragh linkage. The apparatus includes at least one cylinder disposed along a first axis and a piston reciprocable in the at least one cylinder along the first axis. Also included is an orbital crankshaft having a piston crank and an orbital shaft, the piston crank having a first end journaled to the piston and a second end, the second end being secured to the orbital shaft, the orbital shaft extending along a second axis perpendicular to the first axis. An output crank has a first end and a second end, the first end of the output crank being journaled to the orbital shaft. An output shaft is secured to the second end of the output crank, the output shaft being rotatable at an angular velocity about a third axis parallel with the second axis and perpendicular to and intersecting the first axis.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: December 28, 1999
    Inventors: Ilya Gindentuller, Steve Ruiz
  • Patent number: 6007262
    Abstract: A tape printing apparatus is provided. Document data including character data, line feed data and division break-inserting data is input. An editing document formed of the document data is displayed. A position within the editing document is designated. A selected one of registered documents stored is called and inserted into the editing document as document data forming a new division of the editing document, at a predetermined one of a forward position immediately before a desired division within the editing document and a backward position immediately after the desired division, the desired division containing the designated position.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: December 28, 1999
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyasu Kurashina
  • Patent number: 6008854
    Abstract: An input processing section reduces the content of an input video signal according to reduction ratio data, and the reduced video signal is stored in field memories. A display processing section reads a reduced video signal from the field memories to execute window display processing thereto according to video size SIZ data and video position data (X, Y). In this event, an input video clock generator, controlling a writing operation to the field memories, computes video size SIZ data from the reduction ratio data, and writes the SIZ data as a header, along with the reduced video signal, into the field memories via the input processing section. The SIZ data is read to be output to the display processing section and a display video clock generator for controlling reading.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: December 28, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Yutaka Shimizu
  • Patent number: 6005265
    Abstract: A semiconductor integrated circuit device capable of reducing delay of wiring as far as possible is provided. The semiconductor integrated circuit device comprises at least two sets of pairs of signal lines having first polarity and second polarity opposite thereto, wherein the signal line of the first polarity of the signal lines of the second set is disposed at the portion adjacent to the signal line of the first polarity of the signal lines of the first set, the signal line of the second polarity of the first set is disposed at the portion adjacent to the signal line of the first polarity of the second set, and the signal line of the second polarity of the second set is disposed at the portion adjacent to the signal line of the second polarity of the first set.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: December 21, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahiro Kuroda
  • Patent number: 6004887
    Abstract: A semiconductor device includes a substrate, an insulation film formed above the substrate and containing silicon-fluorine bonds, and a titanium-based metal wiring layer formed on the insulation film, the titanium-based metal wiring layer containing fluorine which is diffused from the insulation film and has a fluorine concentration of less than 1.times.10.sup.20 atoms/cm.sup.3.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: December 21, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadashi Matsuno
  • Patent number: 6005521
    Abstract: A microstrip plane antenna and a helical antenna are arranged substantially in line therewith. A base conductor of the microstrip plane antenna is electrically coupled with the helical antenna, thereby allowing stable communications with a orbiting communications satellite in the sky.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: December 21, 1999
    Assignee: Kyocera Corporation
    Inventors: Akihiro Suguro, Hideto Ookita
  • Patent number: 6005732
    Abstract: Device and method for restoring data in a digital VCR is disclosed in which redundancy is provided for detection of more reliable user data. The device optimally equalizes data reproduced in the VCR, and employs comparison detection in restoring the equalized data at the present time. This is accomplished by comparing the equalized data, at the present time, to either an even series prior data or an odd series prior data which has passed through the equalizing part. Determination of the data, at the present time, as not being of a positive polarity where the prior data is determined to be of a positive polarity and determination of the data, at the present time, as not being of a negative polarity where the prior data is determined to be of a negative polarity, thereby prevents the wrong determination applied to the above determination result in restoring the data to the present time.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: December 21, 1999
    Assignee: LG Electronics Inc.
    Inventor: Jung Kyu Lee