Patents Represented by Attorney, Agent or Law Firm Loeb & Loeb LLP
  • Patent number: 7289211
    Abstract: A method of visually quantifying a test material along with an imaging apparatus for practicing the method is disclosed. The method comprises: (a) illuminating the test material at a known angle of incidence with diffuse light of a known and adjustable polarization state; (b) receiving light from the test material with a polarization state modified by the test material; (c) measuring an intensity of the polarization components of the received light for each illuminated pixel substantially simultaneously; (d) calculating the Stokes Vector in two dimensions for each illuminated pixel; and (e) creating an image map for the known polarization state. The method may also include adjusting the known polarization or the incident angle of the diffuse light to create additional image maps. The method and apparatus are intended for use in medical imaging including minimally invasive surgery.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: October 30, 2007
    Inventors: Joseph T. Walsh, Jr., Paul Wu
  • Patent number: 6210412
    Abstract: The present invention is directed to a method of inserting a variety of interbody spinal fusion implants having at least a partially frusto-conical configuration and the instrumentation and methods by which the implants.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 3, 2001
    Inventor: Gary Karlin Michelson
  • Patent number: 6154517
    Abstract: Display is made of the spectrums of the fluorescent X-rays by using the ordinate axis as representing the square root of a fluorescent X-ray intensity and using the abscissa axis as representing the energy of the fluorescent X-rays.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: November 28, 2000
    Assignee: Seiko Instruments, Inc.
    Inventor: Haruo Takahashi
  • Patent number: 6127991
    Abstract: There is proposed is a method of controlling a flat panel display apparatus for multi-gradation display in which a data determination portion and a subfield control portion are provided. Based on a most significant bit or an upper bit of original image data, it is determined in which one of two or more divided gradation groups the original image data is included, to select a combination of subfields in accordance with a gradation-brightness characteristic of the belonging gradation group. Using a complementary relationship with human visibility, a difference in brightness between the gradations in a low-order brightness region is reduced, and a difference in brightness between the gradations in a high-order brightness region is enlarged. Therefore, a density of brightness is uniformly recognized visually over all the brightness regions, and a good quality of display can be obtained.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: October 3, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisao Uehara, Mitsugu Kobayashi, Makoto Kitagawa, Yusuke Tsutsui
  • Patent number: 6124260
    Abstract: Peptides capable of interacting with smooth muscle cells are provided. Peptides are derived from Tenascin-C protein, particularly from the Fbg-L domain of Tenascin-C protein. Peptides of the present invention are useful in inhibiting smooth muscle cell migration. Methods of inhibiting smooth muscle cell adhesion and migration are also provided. Methods of the present invention may be used for treating intimal hyperplasia, restenosis, and atherosclerosis.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: September 26, 2000
    Assignee: Cedars-Sinai Medical Center
    Inventors: Behrooz G. Sharifi, Prediman K. Shah
  • Patent number: 6124142
    Abstract: To provide a minute foreign matter analysis method and device wherein the observation, analysis and estimation of minute foreign matter is permitted by linking the device coordinate of a particle inspection device and those of other analysis devices with by far higher accuracy.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: September 26, 2000
    Assignee: Seiko Instruments, Inc.
    Inventors: Naohiko Fujino, Isamu Karino, Masashi Ohmori, Masatoshi Yasutake, Shigeru Wakiyama
  • Patent number: 6124752
    Abstract: The disclosed semiconductor integrated circuit device can control the threshold thereof without adding any other supply voltages except a drive supply voltage and a ground supply voltage. The semiconductor integrated circuit device comprises: a substrate potential generating circuit operative on the basis of a control signal, for deepening a substrate bias by pumping out charges from a semiconductor substrate when activated, but for setting an output thereof to a high impedance when deactivated; and a switch circuit operative on the basis of the control signal and turned on when the substrate potential generating circuit is deactivated, to set potential of the semiconductor substrate to a supply potential, but turned off when the substrate potential generating circuit is activated.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: September 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahiro Kuroda
  • Patent number: 6122193
    Abstract: Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: September 19, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Shibata, Tomoharu Tanaka, Hiroto Nakai, Toshio Yamamura, Susumu Fujimura
  • Patent number: 6118905
    Abstract: An image processing apparatus detects, in step 1, whether or not differences between currently supplied image data and image data of a previous pixel are more than a predetermined value m, and identifies a border of a computer-created image or a natural image, where a brightness level differs from the remaining area of the image, when the differences are more than the predetermined value m. Conversely, when the differences are less than the predetermined value m, the image processing apparatus checks, in step 2, whether image data at a pixel before and a pixel two before the current pixel are identical with respect to the color components constituting the color image. When the differences are not all zero, it is checked whether or not the image data at a pixel before the current pixel and the image data at the current pixel are all zero. When the image data are not identical, the color image is identified as being a natural image.
    Type: Grant
    Filed: January 19, 1996
    Date of Patent: September 12, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisao Uehara, Mitsugu Kobayashi, Makoto Fujioka, Kenji Saiki, Makoto Kitagawa, Yusuke Tsutsui
  • Patent number: 6116962
    Abstract: A Type III PCMCIA communications card for insertion in a slot in a host computer comprises a housing including a top wall and longitudinal, parallel side walls depending from the top wall, the longitudinal side walls and top wall defining an internal cavity enclosed by a bottom cover panel. The housing further has a forward end, a rear margin and a rear end surface, the rear margin of the housing defining at least one substantially longitudinally oriented receptacle extending forwardly from the rear end surface and sized and configured to receive a standard RJ-type modular plug. A substrate, mounted within the cavity of the housing, supports electronic components for carrying out the communications function.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: September 12, 2000
    Inventor: Ian A. Laity
  • Patent number: 6118469
    Abstract: A thermal printer for printing on a recording medium adapted to travel along a path through the thermal printer includes a frame and a thermal print head supported by the frame, the thermal print head carrying printing elements. A cover hinged to the frame is movable between an open position and a closed position. An elastomeric platen roller is rotatably supported by the cover, the thermal print head and the platen roller being relatively resiliently biased toward each other to urge the printing elements carried by the thermal print head into contact with a recording medium disposed between the thermal print head and the platen roller when the cover is in the closed position.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: September 12, 2000
    Assignee: Seiko Epson Corporation
    Inventor: Hiroaki Hosomi
  • Patent number: 6116157
    Abstract: There are provided a printing method of printing an image of characters, figures or the like on a plate-making surface of a plate-making sheet, and an apparatus therefor. The apparatus feeds a plate-making sheet by a predetermined amount assigned to a forward end of the plate-making sheet when the forward end is detected by a sensor. When a mark for detection provided on the plate-making sheet is detected during the feeding of the plate-making sheet by the predetermined amount assigned to the forward end, the apparatus further feeds the plate-making sheet by a predetermined amount from a position of the plate-making sheet where the mark for detection is detected, to thereby locate the start of an image-forming area of the plate-making sheet. On the other hand, when the mark for detection is not detected, the apparatus continues feeding of the plate-making sheet.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: September 12, 2000
    Assignee: Seiko Epson Corporation
    Inventors: Hitoshi Hayama, Kenji Watanabe, Takanobu Kameda, Tomoyuki Shimmura
  • Patent number: 6114909
    Abstract: A differential amplifier (24) includes a pair of transistors (Q2 and Q9); a differential amplifier 25 includes a pair of transistors (Q3 and Q6). A difference in output currents at the differential amplifier (24) is detected by differential amplifier (25). Then, transistors (Q3 and Q6) in differential amplifier (25) supply currents flowing therein into transistors (Q4 and Q5), whose bases are connected to each other via a capacitor (26). With this arrangement, a difference in DC components between a pair of differential currents flowing in the differential amplifier (25) is obtained at both terminals of the capacitor (26). The obtained voltages at the both terminals of the capacitor (26) are fed back to the input of the differential amplifier (24) via transistors (Q1 and Q8), so that offsets at inputs of the differential amplifier (24) are corrected.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: September 5, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Fukuji Anzai, Hidekazu Inoue
  • Patent number: 6099962
    Abstract: A core-sheath composite yarn characterized in that a softening point of a core component as measured by thermomechanical analysis of JIS K 7196 is at least 20.degree. C. lower than a softening point of a sheath component, and the core component is formed of a substantially amorphous polymer that does not provide a melting point peak as measured by differential thermal analysis of conducting heating in a nitrogen atmosphere at a rate of temperature rise of 10.degree. C./min, and a fabric obtained by using such a composite yarn. This fabric has an excellent shape stability and an excellent water resistance by heat-setting.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: August 8, 2000
    Assignee: Kanebo Ltd.
    Inventors: Ryosuke Sato, Shigeki Honda, Shoichiro Noguchi, Shogo Mutagami
  • Patent number: 6098378
    Abstract: The present invention provides an improved apparatus and method for automatically compressing, rolling, and packaging individual mattresses in a compressed state.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: August 8, 2000
    Inventor: Curtis Wyatt
  • Patent number: 6096234
    Abstract: There is disclosed a cross-linked polymer solid electrolyte and a method of manufacturing the same. A crosslinking agent is added to a block-graft copolymer composed of a polymer block chain A represented by formula I and a polymer block chain B represented by formula II; a high energy ray is irradiated to the block-graft polymer in order to crosslink the entire system; and an nonaqueous electrolytic solution is added to the block-graft polymer. There is also disclosed a composite solid electrolyte for use in a solid electrochemical element. The composite solid electrolyte includes an electrically insulating material, an alkali metal salt, a block-graft copolymer composed of a polymer block chain A represented by formula I and a polymer block chain B represented by formula II, and an aprotic organic solvent.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: August 1, 2000
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Toru Nakanishi, Kazuhiro Hirahara, Toshinobu Ishihara, Yoshinobu Isono, Atsushi Takano
  • Patent number: 6097038
    Abstract: There is provided a semiconductor device in which a semiconductor layer and a gate electrode are formed with a gate insulating layer between then and in which a region of the semiconductor layer opposite to the gate electrode is used as a channel region. On the semiconductor layer, an insulating protection film and an amorphous semiconductor layer are successively formed. The protection film covers at least the channel region of the amorphous semiconductor layer, and annealing is applied to the amorphous semiconductor layer, thereby converting the amorphous semiconductor layer into the polycrystal semiconductor layer. A portion to be the channel region of the amorphous semiconductor layer is covered by the protection film. Therefore, even when exposed to the atmosphere due to annealing, surface contamination can be prevented and a semiconductor device having satisfactory characteristics can be obtained. A thickness d of the protection film is set to be nearly ".lambda./4 n" for a wavelength .lambda.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: August 1, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Yushi Jinno
  • Patent number: 6094373
    Abstract: This invention is made to reduce the circuit area and shorten the testing time by simplifying the construction of the control circuit and reducing the number of commands. In the automatic programming operation, PVOK is set to "0", EVOK and LCKOK are set to "1", and a memory cell is selected by an address latched in the address register. That is, the subroutine of a pre-program operation is effected with the address fixed. None of the subroutines of an erase operation and convergence operation are effected. In the erase operation, PVOK, EVOK and LCKOK are all set to "0" and memory cells are sequentially selected by the internal address of the address counter. That is, each of the memory cells selected by the internal address is subjected to the pre-program, erase and convergence operations.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: July 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi Saito
  • Patent number: 6092239
    Abstract: A foldable cap is disclosed made from a flat semi-rigid material cut into a plurality of middle panels for forming the crown portion of a cap and two lateral panels for forming the brim of the cap. Each of the middle panels and the lateral panels have a free end and a fixed end connected to the remainder of the uncut semi-rigid material. The middle panels of the cap are folded and overlapped proximate their free ends to form a cupped area for receiving a user's head. The angled lateral portions are then bent toward each other to overlap at least one free end of the middle panels so as to form a brim for the cupped area.
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: July 25, 2000
    Inventors: Eduard Pogrebitsky, Michael Guz
  • Patent number: RE36904
    Abstract: A network adapter configured to functionally connect a local area network cable to a personal computer bus via the computer's standard parallel port. The adapter includes a substantially fully enclosed housing having first and second external connection respectively configured to mate with a computer's parallel port connector and with a network cable. The adapter is primarily comprised of (1) network interface circuitry for transmitting data packets to and receiving data packets from a local area network and (2) input/output circuitry for bidirectionally transferring data bytes between the network interface circuitry and a computer's parallel port.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: October 3, 2000
    Assignee: Xircom, Inc.
    Inventor: Dirk I. Gates