Patents Represented by Attorney Lynn Morgan & Finnegan, LLP Augspurger, Esq.
  • Patent number: 5828894
    Abstract: Array processors are made by assembling individual microcomputer elements into an array. Larger arrays are called massively parallel processors. Some can operate in SIMD, while others can operate in MIMD, or SIMD and MIMD in special configurations. In a SIMD array of processors, there is a need to partition the processors into groups related to the type of problem they contain. When the grouping is the result of a computation within the processing element, it is desirable that each processing element be capable of assigning itself to a group, or maybe several groups. This disclosure describes a means of assigning processing elements to groups as an array function conducted in parallel by all active processing elements in the array, and then using grouping to select certain processing elements for a computation that is unique to the group.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: October 27, 1998
    Assignee: International Business Machines Corporation
    Inventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge
  • Patent number: 5825678
    Abstract: A new Test FP Data Class operation is provided which utilizes a 12-bit mask to determine to which of the 12 possible data classes a floating point number belongs and sets a condition code accordingly. As preferably embodied, a typical IBM System 390 instruction format is adapted to implement a Test FP Data Class operation. The class and sign of the first operand are examined to select one bit from the second-operand address. A condition code of 0 or 1 is set according to whether the selected bit is 0 or 1. The second-operand address is not used to address data; instead, individual bits of the address are used to specify the applicable combinations of operand calls and sign.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: October 20, 1998
    Assignee: International Business Machines Corporation
    Inventor: Ronald M. Smith
  • Patent number: 5815723
    Abstract: A parallel array computer provides an array of processor memory elements interconnected for transfer of data and instructions between processor memory elements. Each of the processing elements has a processor coupled with a local memory. An array controller is provided for controlling the operation of the array of processor memory elements. Each of the processor memory elements has a plurality of local autonomous operating modes and is adapted to interpret instructions from the array controller within the processor memory element.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: September 29, 1998
    Assignee: International Business Machines Corporation
    Inventors: Paul Amba Wilkinson, Thomas Norman Barker, James Warren Dieffenderfer, Peter Michael Kogge
  • Patent number: 5774735
    Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register. An automatic wake-up mechanism may also be provided to keep the array active during extended periods of non-use.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 30, 1998
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Meaney, Adrian E. Siegler
  • Patent number: 5752264
    Abstract: A hierarchical cache architecture that reduces traffic on a main memory bus while overcoming the disadvantages of prior systems. The architecture includes a plurality of level one caches that are of the store through type, each level one cache is associated with a processor and may be incorporated into the processor. Subsets (or "clusters") of processors, along with their associated level one caches, are formed and a level two cache is provided for each cluster. Each processor-level one cache pair within a cluster is coupled to the cluster's level two cache through a dedicated bus. By configuring the processors and caches in this manner, not only is the speed advantage normally associated with the use of cache memory realized, but the number of memory bus accesses is reduced without the disadvantages associated with the use of store in type caches at level one and without the disadvantages associated with the use of a shared cache bus.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: May 12, 1998
    Assignee: International Business Machines Corporation
    Inventors: Michael Andrew Blake, Carl Benjamin Ford, III, Pak-kin Mak
  • Patent number: 5734921
    Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32 K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: March 31, 1998
    Assignee: International Business Machines Corporation
    Inventors: Michael Charles Dapp, James Warren Dieffenderfer, Richard Ernest Miles, Richard Edward Nier, Vincent John Smoral, James Robert Stupp