Patents Represented by Attorney, Agent or Law Firm Marc S. Hanish
  • Patent number: 6820123
    Abstract: More effective load balancing by a Server Load Balancer may be achieved by implementing extended Server Load Balancing information in a server. The extended Server Load Balancing information includes a special listing of “hot” objects, or objects that have been designated for special handling by the Server Load Balancer. In order to determine which objects on a server are “hot” at any particular point in time, the available throughput for the server is determined. This is then multiplied by a “hotness” percentage, resulting in an Object Threshold Value (OTV). Each of N objects is then assigned an Object Request Value (ORV), the N objects determined by taking the N objects utilizing the most bandwidth. The ORVs are then compared with the OTV, and any of the objects whose ORV exceeds the OTV are labeled as “hot”. Finally, information on the “hot” objects is communicated to the Server Load Balancer (SLB) for special handling.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: November 16, 2004
    Assignee: Cisco Technology, Inc.
    Inventor: Douglas Gourlay
  • Patent number: 6771665
    Abstract: A solution for matching RADIUS request packets with corresponding RADIUS response packets when the number of simultaneous outstanding requests is greater than 256 involves using a sixteen-octet authenticator field in each packet. For each response packet that arrives, the identifier of the packet is compared in turn with the identifier of each outstanding request packet. If the identifiers match, the authenticators are then compared. If the results of the comparison indicate a match, the packet is accepted and no further processing of the outstanding requests is required. Otherwise, a search of the outstanding request packets is continued. This solution allows for more than 256 simultaneous outstanding RADIUS requests and only encounters a mismatch or ambiguous match with a probability of one in 3.4×1038 packets.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: August 3, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Scott K. Reed, Gregory Weber, Mark Eklund, Robert Sargent, Steven J. Rich
  • Patent number: 6765907
    Abstract: An apparatus is provided which processes upstream multicast packets and downstream multicast packets in a manner such as to avoid the problem of multicast echo which is generated from a host gateway. For upstream multicast packets, a method is provided which includes: extracting the source network address from the upstream multicast packet; storing said source network address in a table corresponding to the destination host gateway of the packet; and forwarding the upstream multicast packet to the destination network address.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: July 20, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Xi Xu, Shuxian Lou, Shujin Zhang
  • Patent number: 6732178
    Abstract: A system manages communications between a user and a network by receiving a user request for access to a network file during a user network connection session with a connecting network, determining whether the user has a connected user session state or a disconnected user session state with respect to a portal server, responding to a disconnected user session state by determining a user identity that specifies a physical location for the user and providing the user with a redirected page for display in a user graphical interface program in accordance with the determined user physical location user identification and in accordance with service selection information, and then changing the user session state to a connected state, and responding to a connected user session state by routing the user request for access to the network file to a network server.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: May 4, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Peter Van Horne, Edwin James Van Horne
  • Patent number: 6728738
    Abstract: The analysis of the lifetime of objects in a garbage-collected system may be accomplished quickly and effectively using reference counts and cyclic garbage analysis. A reference count is maintained for each of the objects to indicate the number of incoming pointers. Each time the graph structure is altered, the reference counts are updated. Timestamps are recorded each time the reference count for objects change. If a reference count goes to zero, the corresponding object may be indicated as dead. A garbage collection need only be run once (perhaps at the end), and after it is run the system may indicate which objects are cyclic garbage. The timestamps for objects which are cyclic garbage are then reviewed in reverse chronological order. For each timestamp found, the corresponding object and any object reachable from the corresponding object are indicated as dead. These objects are then removed from the set of cyclic garbage.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: April 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Mario Wolczko, Antonio Cunei
  • Patent number: 6708324
    Abstract: Extensible automated testing software provides reliability, user extendibility, scalability, and multiple simultaneous testing support through the use:of modules which the user may employ to set up and run test scripts. One or more job files are passed to an execution harness, which then starts a System Runner Process on a host specified in the one or more job files if one has not already been started. A connection is then made between the execution harness and the system runner process and one or more Test Runner Processes are spawned. These Test Runner Processes may be spread out over various hosts. Each of these Test Runner processes calls procedures to execute one test script at a time. Since multiple instances of the software may be run simultaneously, this allows the software to properly manage multiple tests running on multiple hosts being executed by multiple users.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: March 16, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Jeffrey P. Solloway, Jay W. Yang, Ying He
  • Patent number: 6683626
    Abstract: Scrolling through one or more focusable and/or non-focusable items may be accomplished by: scrolling the display a set number of pixels in said direction if the cursor location is on a non-focusable item and an end border in said direction of said non-focusable item is not currently shown on the display; moving the cursor location to a next focusable item in said direction and scrolling the display enough in said direction to display said next focusable item if the cursor location is on a non-focusable item and an end border in said direction of said non-focusable item is currently shown on the display or if the cursor location is on a focusable item and a next item in said direction is a focusable item or if the cursor location is on a focusable item, the next item in said direction is a non-focusable item, and an end border in said direction of said non-focusable item is currently shown on the display; and moving the cursor location to a next non-focusable item and scrolling the display in said direction if
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: January 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventor: Suzanne L. Abellera
  • Patent number: 6675372
    Abstract: Counting events during the execution of one or more instructions in a computer system may be accomplished by maintaining a non-speculative counter for counting events occurring in non-speculative instructions, as well as a separate speculative counter for counting events occurring in speculative instructions. Event counters may be used to count individual events occurring during the processing of instructions. When the instruction has been completed, the amount in the event counter corresponding to a particular event for that instruction is added to the amount in the speculative counter corresponding to the event. Then, any retirable instructions are retired. Once an instruction is retired, it is no longer speculative, allowing the amount in the speculative counter to be decremented and the amount in the non-speculative counter to be incremented by the amount in any event counters corresponding to retirable instructions.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: January 6, 2004
    Assignee: Sun Microsystems, Inc.
    Inventor: Peter C. Damron
  • Patent number: 6675338
    Abstract: Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (LFSR) that the microchip is in the burnin stage. The LFSR then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal state of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggled without the use of an external memory for the burnin system.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: January 6, 2004
    Assignee: Sun Microsystems, Inc.
    Inventor: Farideh Golshan
  • Patent number: 6654893
    Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: November 25, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Jaya Prakash Samala
  • Patent number: 6654017
    Abstract: The middle of line segments may be drawn on a computer display using an iterative method that reduces the number of calculations required. The process is repeated for each column. The first pixel is plotted according to a formula that allows the first pixel to best represent the location of the line in the column. A second pixel is then plotted either above, below, to the left of, or the right of the first pixel depending on the direction of the line. A normalized intensity value between 0 and 1.0 is then assigned to the first pixel according to the amount of area above, below, to the left of, or the right of the line in the first pixel depending on the direction of the line. This value may be assigned using a variable computed in plotting the first pixel. A normalized intensity value for the second pixel equal to 1.0 minus the normalized intensity value of the first pixel may then be assigned. Finally, the first and second pixels are shaded according to the normalized intensity values.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: November 25, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Gunawan Ali-Santosa
  • Patent number: 6654952
    Abstract: Region based optimization may be accomplished by creating dependence graphs for each block and then incrementally computing a single dependence graph for the region. First dependence DAGs are created for each block in the region. This includes defining incoming and outgoing dangling edges for each block. Each dependence DAG is then linked as a control flow graph. Examining of each incoming dangling edge within each block of the region then takes place, with the process traversing each path along the control flow graph in reverse, attempting to match each incoming dangling edge with a corresponding incoming or outgoing dangling edge, stopping only if an outgoing match is found, the same block is examined twice, or the top of the region is found.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: November 25, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Sreekumar Ramakrishnan Nair, Peter C. Damron
  • Patent number: 6636230
    Abstract: Starting and ending caps of smooth line segments may be drawn on a computer display without complicated calculations and avoiding the use of inverse square root calculations by drawing the caps using rectangles. The direction of the line segment may be determined, and using the direction certain pixels in a four-pixel grouping may be selectively illuminated. The normalized intensity values of the illuminated pixels may be determined by computing an x-fraction and a y-fraction, representing the distance in the x-direction and y-direction between a sample origin point in a corner of the four-pixel grouping and the closest corner of a region covered by the mathematical origin or endpoint corrected for the thickness of the line segment. It is generally preferable for only two pixels to be illuminated for each cap, the pixels chosen according to a formula ensuring that there are no perception problems when two smooth line segments share a common mathematical origin or endpoint.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: October 21, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Gunawan Ali-Santosa
  • Patent number: 6636231
    Abstract: Starting and ending caps of smooth line segments may be drawn on a computer display without complicated calculations and avoiding the use of inverse square root calculations by drawing the caps using rectangles. The direction of the line segment may be determined, and using the direction certain pixels in a four-pixel grouping may be selectively illuminated. The normalized intensity values of the illuminated pixels may be determined by computing an x-fraction and a y-fraction, representing the distance in the x-direction and y-direction between a sample origin point in a corner of the four-pixel grouping and the closest corner of a region covered by the mathematical origin or endpoint corrected for the thickness of the line segment. It is generally preferable for only two pixels to be illuminated for each cap, the pixels chosen according to a formula ensuring that there are no perception problems when two smooth line segments share a common mathematical origin or endpoint.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: October 21, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Gunawan Ali-Santosa
  • Patent number: 6606094
    Abstract: A method and apparatus for horizontally expanding a video graphics adapter (VGA) text character display image to fully fill the screen of a flat panel display. Cell lines for each character are remapped to provide expanded cell lines. The flat panel apparatus includes a video memory for storing the character code, attribute data and font data, a character generator for generating character font data based on the character code, a lookup table for providing expanded cell lines, and an attribute controller for combining the font data and the attribute data for output to a flat panel display.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventor: Morris E. Jones, Jr.
  • Patent number: 6598066
    Abstract: A carry-out bit generator determines if a bit pattern from two positive numbers matches one of the patterns for which a carry-out bit would be generated in addition. These patterns include a TnG pattern and a Tm pattern (with a carry-in). Superscript n represents a number between zero and m−1, superscript m represents the number of registers, T represents a 0/1 or 1/0 pair and G represents a 1/1 pair.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: July 22, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Michael L. Ott
  • Patent number: 6594278
    Abstract: A method of transmitting delay sensitive information over Internet Protocol (IP) over Frame Relay including storing the information in an IP packet, storing the IP packet in a sub-frame, storing a special symbol representing that the frame is delay sensitive in the sub-frame, storing the sub-frame in a frame, storing a network layer protocol identification representing that the frame contains IP information in the frame, and transmitting the frame over a Frame Relay Network, distinguishing delay sensitive information from non-delay sensitive information by examining the special symbol. Additionally, in systems using the FRF.12 or similar fragmenting standard, the special symbol may be stored in the header of the fragment.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: July 15, 2003
    Assignee: Cisco Technology, Inc.
    Inventor: Mihyar Baroudi
  • Patent number: 6587468
    Abstract: A method for replying to a DHCP request packet is provided which allows a DHCP server to forward its reply packet directly back to the requester, thus permitting a gateway or similar device to make a DHCP request on behalf of a client. A reply to sender options field in the DHCP request packet is used to signify when the reply packet should be sent directly back to the requester.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: July 1, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: Maria Alice Dos Santos, Shujin Zhang
  • Patent number: 6583788
    Abstract: A method for rendering a line segment extending in the positive-x direction and positive-y direction on a computer display given a starting point and an ending point, the starting point having the form (xs, ys) and the ending point having the form (xe, ye). In this method, &Dgr;x and &Dgr;y are computed using the formula &Dgr;x=|xe−xs| and &Dgr;y=|ye−ys|, respectively. Then dt(0)=(yf*&Dgr;x)−(xf*&Dgr;y) is computed, where xf is the fractional portion of xs and yf is the fractional portion of ys, which allows for more precision. If the line segment extends in the postive-x and positive-y directions, then for each column n containing a portion of said line segment the process: plots said current pixel if dt(n)<=0.5*&Dgr;x and plotting the pixel above said current pixel if dt(n)>0.5*&Dgr;x; moves said current pixel to the right one pixel if dt(n)<=0.5*&Dgr;x and moves said pixel to the right and up one pixel if dt(n)>0.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: June 24, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Gunawan Ali-Santosa
  • Patent number: 6578168
    Abstract: A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: June 10, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Ishwardutt Parulkar, Sridhar Narayanan, Gajendra P. Singh, Jaya Prakash Samala