Abstract: A method and apparatus for web-based tool management are implemented. A tool object model provides a logical representation of the physical tool. The tool object model defines a hierarchical set of tool objects that characterize the tool, and additionally a set of method for performing actions on the tool objects. These actions also correspond to operations, which may include reporting as well as processing tasks, performed by the tool. A user may remotely control and monitor a tool using a conventional web browser. For example, a user may execute methods of the tool object model, or obtain detailed information about a tool object. User actions are passed to a server by embedding them in hypertext transfer protocol (HTTP) requests. The server receives the HTTP request, and passes the request to a corresponding page server in accordance with the action requested. Depending on the action requested, the page server may generate a web page in response, or may invoke a method of the tool object model.

Abstract: Methods for controlling a Power On Reset (POR) circuit in an Integrated Circuit (IC) are presented. In one embodiment, a method includes an operation for gating a test POR signal configured to selectively disable an output of a POR circuit, and an operation for programming a fuse. The programming of the fuse includes operations for disabling the signal path of the test POR signal, and for enabling the output of the POR circuit. In another embodiment, the signal path of the test POR signal includes a pass gate, where permanently disabling the signal path is performed by disconnecting the pass gate.

Abstract: Methods and computer programs for determining the top most critical timing paths in an integrated circuit (IC) based on a timing graph of registers and combinational nodes in the IC are provided. One method generates the most critical path to each destination register and invokes a function to calculate the next critical path in each destination register a number of times according to the number of top most critical paths desired. The method uses recursion to calculate critical paths on the different nodes by recursively calling a function to calculate the next critical path on a fan-in node, where the fan-in node corresponds to the node which last contributed a critical path. Further, the most critical path to the node is selected in the recursive function. The critical paths are used to determine if the IC is stable under the analyzed clock frequency.

Abstract: An image processing method involves processing image data indicative of an image represented with a prescribed number of input tones by each of pixel groups composed of a plurality of print pixels, and generating dot data representing a status of dot formation on each of the print pixels to be formed on a print medium. The method includes preparing a first conversion table and a second conversion table, determining the pixel group tone value in response to the input tone value corresponding to the pixel group, converting the determined pixel group tone value into the code values for each of the pixel groups, by referring to the first conversion table, decoding the acquired code value into the output dot arrangement for each of the pixel groups, by referring the second conversion table, and outputting the dot data in response to the output dot arrangement.

Abstract: An apparatus, system and method for preventing premature drying of a surface of a substrate between fabrication operations includes receiving a substrate for cleaning, performing wet cleaning operations to the surface of the substrate to remove contaminants and fabrication chemistries left behind during one or more fabrication operations from the surface of the substrate, identifying a saturated gas chemistry and applying the identified saturated gas chemistry in a transition region such that the surface of the substrate exposed to the saturated gas chemistry in the transition region retains the moisture thereby preventing the surface of the substrate from premature drying. The saturated gas chemistry is applied between two subsequent wet-cleaning operations.

Abstract: A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features within the gate electrode level region extend over the p-type diffusion regions to form respective PMOS transistor devices. Also, some of the conductive features within the gate electrode level region extend over the n-type diffusion regions to form respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.

Abstract: A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that is an integer multiple of the clock rate. A training mechanism using training data detects time skew between host clock and bit stream, and a digital skew compensation mechanism compensates, substantially in real time, for the skew and for variations in the skew that may occur with the passage of time, in accordance with a vote among at least three samples of a bit of the bit stream, subsequent sampling being retarded or advanced if, respectively, an early or late sample is in disagreement with the vote. Preferably, the compensation value is selected from at least four possible compensation values, and can be stored in a memory to hasten subsequent restarts of the system.

Abstract: The image output system of the invention collects a preset number of adjacent pixels to one pixel group to divide a number of pixels constituting an image into multiple pixel groups and specifies a pixel group tone value as a representative tone value of each pixel group. The image output system refers to a conversion table to generate dot number data of each pixel group. The conversion table stores dot number data, which represents number of dots to be created in one pixel group, in relation to a combination of a pixel group classification number allocated to each pixel group and the specified pixel group tone value of the pixel group. The image output system then refers to a priority order of pixels representing potentials of dot creation in respective pixels of one pixel group, determines the positions of dot-on pixels in each pixel group according to the generated dot number data of the pixel group, and actually creates dots according to the determined positions of the dot-on pixels.

Abstract: A method and system for designing an optimized specification of an integrated circuit (IC) is provided. The IC comprises a plurality of cells, and each of the cells comprises a plurality of transistors. The method includes preparing a linewidth map of at least one device of the plurality of devices, performing a topography-aware analysis of the at least one device based on the linewidth map, and designing the optimized specification of the IC based on the topography-aware analysis. In another embodiment, a method for estimating a leakage power of at least one device in an IC is provided. The method includes determining a defocus and a pitch value, determining a linewidth value based on the defocus and pitch value, and estimating the leakage current and/or leakage power based on the linewidth value.

Abstract: A system and method for forming a planar dielectric layer includes identifying a non-planarity in the dielectric layer, forming one or more additional dielectric layers over the dielectric layer and planarizing at least one of the additional dielectric layers wherein the one or more additional dielectric layers include at least one of a spin-on-glass layer and at least one of a low-k dielectric material layer and wherein each one of the one or more additional dielectric layers having a thickness of less than about 1000 angstroms and wherein the one or more additional dielectric layers has a total thickness of between about 1000 and about 4000 angstroms.

Abstract: A method and system for determining an intensity value of an interaction with a computer program is described. The method and device includes capturing an image of a capture zone, identifying an input object in the image, identifying an initial value of a parameter of the input object, capturing a second image of the capture zone, and identifying a second value of the parameter of the input object. The parameter identifies one or more of a shape, color, or brightness of the input object and is affected by human manipulation of the input object. The extent of change in the parameter is calculated, which is the difference between the second value and the first value. An activity input is provided to the computer program, the activity input including an intensity value representing the extent of change of the parameter. A method for detecting an intensity value from sound generating input objects, and a computer video game are also described.

Abstract: A method is provided for removing a residual fluid remaining at a point of contact between a substrate support member and a back surface of a substrate being prepared by a proximity head. According to the method, the proximity head is applied onto the back surface of the substrate and the substrate support member being held by a carrier. The substrate support member is heated after the substrate support member passes the proximity head. The heating of the substrate support member is discontinued once the residual fluid has substantially evaporated.

Abstract: Broadly speaking, the embodiments of the present invention provide an improved chamber cleaning mechanism, apparatus and method. The present invention can also be used to provide additional knobs to tune the etch processes. In one embodiment, a plasma processing chamber configured to generate a plasma includes a bottom electrode assembly with an inner bottom electrode and an outer bottom electrode disposed outside of the inner bottom electrode, wherein the inner bottom electrode is configured to receive a substrate. The plasma processing chamber also includes a top electrode assembly with a top electrode, wherein the top capacitive electrode is disposed directly above the inner and outer bottom electrodes.

Abstract: In an example embodiment, an online advertising management platform receives a login that identifies a user as a user allowed access to an account maintained by the platform. The platform displays a toolbar having a textbox that allows the user to search for data relating to all accounts to which the user has access. The platform displays a combo box after the user enters a fixed number of characters in the textbox. The combo box includes a list of descriptions of each data object that is accessible and that is relevant to the fixed number of characters. The platform locates the combo box contiguous to the toolbar over some but not all of the view displaying the data relating to the order. The platform displays a data object, rather than a page of search results, after the user clicks a description of a data object from the combo box.

Abstract: Provided is a distributed test system and method for electrical devices that features bifurcated testing and analysis of test results for electrical devices by aggregating test results from multiple testing systems to a centralized server where analysis of test data is undertaken. The system includes a plurality of testing systems, each of which is configured to operate test software to provide electrical stimuli to devices under test (DUTs) and obtain measured metrics indicative of actual operational characteristics (AOCs) of the DUTs. A decision support system (DSS) is selectively placed in data communication with the plurality of testing systems to receive the measured metrics from each of the plurality of testing systems. The DSS is configured to operate on software and compare desired metrics, indicative of desired operational characteristics (DOCs) of each of the DUTs, with the measured metrics and provide a plurality of operational characteristic determinations (OCDs).

Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes a storage circuit coupled to receive a data signal, a clock input signal and a reset signal. The storage circuit may be used to generate a clock signal. The reset signal is supplied by a reset circuit. The reset circuit may include one or more logic gates to generate the reset signal. The reset circuit receives a phase shifted version of the clock input signal and the reset signal is generated based on the phase shifted version of the clock input signal. In one embodiment, the reset signal is a series of pulses generated at specific intervals to shift the output of the storage circuit from logic high level to logic low level.

Abstract: A controller for one type of NAND flash memory device that emulates another type of NAND flash memory device. The controller may include a host NAND interface to receive host data from a NAND host device, and a data aggregator for aggregating the host data with complementary data, to thereby create device data that is storable in a device page of an array of NAND flash memory cells of the NAND flash memory device. After creating the device data the controller writes the device data into a device page of the NAND flash memory cells. The controller also includes a data parser to parse host data from device data when data read operations are executed by the controller. If required, the controller uses the data parser to parse complementary data from device data to create device data when data writing operations are executed by the controller.

Abstract: Methods configure a proximity head for conditioning fluid flow relative to a proximity head in processing of a surface of a wafer by a meniscus. The methods configure the head in one piece while maintaining head rigidity even as the head is lengthened for cleaning of large diameter wafers. The one-piece head configuring separates main fluid flows from separate flows of fluid relative to the wafer surface, with the separation being by a high resistance fluid flow configuration, resulting in substantially uniform fluid flows across increased lengths of the head in a unit for either fluid supply or return.

Abstract: A method for optimizing pin selection for an integrated circuit is provided. Pin locations are mapped to a vector. The mutual inductive relationships between pins of the integrated circuit are captured into a matrix. The matrix contains the data of how a signal state of each pin is affected by the toggling of other pins within the I/O bank. The pin locations and the crosstalk matrix are combined to characterize the impact of the crosstalk on the pins for the pin placement. Thereafter, a user may decide to alter the pin placement or alter the sampling interval for the pin to avoid sampling the pin when the crosstalk may affect the signal integrity. The method may be applied for multiple simultaneous switching noise cause mechanisms impacting the signal integrity. In this embodiment, a worst case cause mechanism from the individually quantified cause mechanisms is determined by comparing an impact of each of the cause mechanisms.

Abstract: A pragma is used to pass circuit type information to a Computer Aided design (CAD) tool. The CAD tool then selects an alternate synthesis or timing algorithm based on the circuit type, and a circuit design for use in an electronic device is created. Practical applications include using alternate algorithms specific to different circuit types, such as, Cyclic Redundancy Checks (CRC), bus arbiters, state machine encoders, barrel shifters, preferential cores, and legacy circuits. One embodiment generates informative messages for the designer once the circuit type is known and the analysis is performed. Another embodiment generates pragmas that can be later used by circuit designers in future circuit designs.