Patents Represented by Attorney McDermott Will & Emery LLP
  • Patent number: 8351783
    Abstract: The chromatic dispersion of an optical component is measured with high accuracy using a simple set-up, which includes a pump light source, a probe light source, and a measuring means. Pump light having a wavelength ?pump and probe light having a wavelength ?probe is propagated through an optical component, with the wavelength ?probe being apart from the wavelength ?pump by a given frequency. The generation efficiency of the idler light with respect to the wavelength ?pump is calculated by measuring the power of idler light having a wavelength ?idler output from the optical component, and by seeking the pump light wavelength for making the generation efficiency a local extreme value, the chromatic dispersion of the optical component is calculated from the result of calculation of phase mismatch among the pump light wavelength having such wavelength as sought, the corresponding probe light wavelength, and the corresponding the idler light wavelength.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaaki Hirano, Toshiki Taru
  • Patent number: 8349398
    Abstract: An aerosol spray apparatus and a method of forming a film using the aerosol spray apparatus are disclosed. The aerosol spray apparatus in accordance with an embodiment of the present invention includes: a carrier gas injection unit, which forms carrier gas by vaporizing liquefied gas and increases the pressure of the carrier gas; an aerosol forming unit, which forms an aerosol by mixing the carrier gas with powder; and a film forming unit, which sprays the aerosol in a normal pressure environment such that the film is formed on the surface of the board. The apparatus can perform a coating process with no restriction of the type and size of powder, simplify the process because the film can be formed in a normal temperature and pressure environment, and control a wide range of film thickness in a short time.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: January 8, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hee-Sung Choi, Kwang-Su Kim, Hoo-Mi Choi, Tae-Sung Kim, Mi-Yang Kim, Hyun-Ho Shin
  • Patent number: 8347554
    Abstract: A hinge enabling a plurality of hold-stay members to automatically lock when the door is fully open, increasing the durability of the hinge, and enabling easy release of the hold-stay members. A hinge includes a one-side hinge plate, a plurality of opposing-side hinge plate portions provided along the lengthwise direction of the hinge plate and supported by it, and an open-angle limiting mechanism for stopping, at a specific angle, opening movement of the opposing-side hinge plate portions.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: January 8, 2013
    Assignee: Caterpillar SARL
    Inventors: Ryoji Uto, Takahiro Goto
  • Patent number: 8351253
    Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hideto Hidaka
  • Patent number: 8350655
    Abstract: Axisymmetric solid of revolution derivable from section at FIG. 5 is generally toroidal with electric current(s) in windings 110, 160 preferably flowing circumferentially along major circle(s) during power coupling device operation. Current(s) in windings 110, 160; current(s) in half-shields 120, 170; and the volume of space swept out by shield airgap(s) 101 emerge from plane of paper perpendicularly at FIG. 5 but as these emerge therefrom they curve to follow toroidal major circle(s). Cores 115, 165 preferably shunt and align magnetic flux such that magnetic field lines escape therefrom primarily only in region(s) of core airgap(s) and such that magnetic flux loops lie in planes of toroidal minor circle(s).
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: January 8, 2013
    Assignee: Analogic Corporation
    Inventor: John M. Dobbs
  • Patent number: 8351180
    Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: January 8, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ghyu Ahn, Byoung Hwa Lee, Min Cheol Park, Sang Soo Park, Dong Seok Park
  • Patent number: 8350342
    Abstract: A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-conductivity type first impurity being diffused in the extension diffusion layers, and source and drain diffusion layers provided in regions farther outside than the respective extension diffusion layers of the semiconductor region and having junction depths deeper than the respective extension diffusion layers. At least one of the extension diffusion layers on both sides of the gate electrode contains carbon.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: January 8, 2013
    Assignee: Panasonic Corporation
    Inventor: Taiji Noda
  • Patent number: 8349201
    Abstract: A method of processing a SOI substrate to form a groove in the SOI substrate in which a silicon layer is stacked on both sides of an oxide layer is disclosed. In accordance with an embodiment of the present invention, the method includes dividing a portion of the silicon layer, in which the groove is to be processed, into a plurality of unit portions, performing dry etching on certain portions of the plurality of divided unit portions such that the oxide layer is exposed and removing remaining portions of the plurality of divided unit portions by removing the oxide layer.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: January 8, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chung-Mo Yang, Jae-Woo Joung, Young-Seuck Yoo
  • Patent number: 8349161
    Abstract: Bubbles can be removed regardless of an individual difference of a pump to fill an electrophoresis medium into a capillary. Of flow passages formed between an inner side surface of a container for accommodating the electrophoresis medium and a side surface of a plunger, one of the flow passages causing an electrophoresis medium to be easily stagnant is formed to have the cross-sectional area larger than the cross-sectional area of the other flow passage on the opposite side. In other words, the flow passage portion causing the electrophoresis medium to be easily stagnant is formed in such a manner as to increase a flow amount of the electrophoresis medium. This can eliminate a region having an extremely small amount of electrophoresis medium flow in the pump.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: January 8, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takashi Gomi, Ryoji Inaba, Taro Nakazawa, Takeshi Ohura, Mari Kotoura
  • Patent number: 8350531
    Abstract: A secondary battery charge control method includes: a charge control step of executing charging by supplying a charge current to a secondary battery; a charge information acquisition step of acquiring information relating to the charging executed in the charge control step; a storage step of storing the information acquired in the charge information acquisition step as charge data; and a charge inhibition determination step of determining whether to inhibit the charging in the charge control step on the basis of the charge data of a previous cycle that have been stored in the storage step when charging in the charge control step is started again after charging in the charge control step has been completed.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: January 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Naohisa Morimoto, Toshihiro Inoue
  • Patent number: 8350609
    Abstract: The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Araki, Atsuhiko Ishibashi
  • Patent number: 8343896
    Abstract: Methods are provided comprising providing a sealant composition comprising an aqueous fluid, a diutan composition, at least one gel system, and a leak off prevention material; introducing the sealant composition into a well bore penetrating the subterranean formation; and allowing the sealant composition to form a seal.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: January 1, 2013
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Larry S. Eoff, Richard W. Pauls
  • Patent number: 8343657
    Abstract: In a lithium secondary battery using a negative electrode having a negative electrode mixture layer formed on a surface of a negative electrode current collector, the mixture layer made of a binder and negative electrode active material particles of silicon and/or a silicon alloy, charge-discharge cycle performance is improved without degrading the capacity per unit volume, by making the negative electrode mixture layer sufficiently adhere to the negative electrode current collector. The negative electrode has a negative electrode mixture layer composed of a binder and negative electrode active material particles of silicon and/or a silicon alloy. The negative electrode mixture layer is formed on a surface of the negative electrode current collector by sintering. Negative electrode active material particles are partially embedded in the negative electrode current collector.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: January 1, 2013
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroshi Minami, Atsushi Fukui, Yasuyuki Kusumoto
  • Patent number: 8344320
    Abstract: A lens adjustment method and a lens adjustment system which adjust a plurality of multi-pole lenses of an electron spectrometer attached to a transmission electron microscope, optimum conditions of the multi-pole lenses are determined through simulation based on a parameter design method using exciting currents of the multi-pole lenses as parameters.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: January 1, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Shohei Terada, Yoshihumi Taniguchi, Kazutoshi Kaji
  • Patent number: 8344522
    Abstract: The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at least part of the surface of the Sn alloy. The Au covering is a film that covers and coats at least part of the surface of the Sn alloy. As a preferable mode, the Au coating forms a netlike structure on the surface of the Sn alloy. The thickness of the Au coating is, for instance, 1 to 5 ?m.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: January 1, 2013
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideki Mizuhara, Hajime Kobayashi, Toshiya Shimizu
  • Patent number: 8345470
    Abstract: A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Katsuji Satomi, Toshio Terano, Kazuhiro Takemura, Marefusa Kurumada
  • Patent number: 8347349
    Abstract: Systems and methods for configuring browser policy settings on client computing devices are provided. In some aspects, a method includes receiving login credentials from a client computing device. The client computing device includes a browser. The method also includes transmitting browser policy data associated with the login credentials to the client computing device. The browser policy data identifies browser policy settings to be installed on the browser. The browser policy settings identified by the browser policy data include four or more of: compliance settings, behavioral settings, browser/software applications, permission to access one or more websites, restrictions on accessing one or more websites, read permission in a remote document storage unit accessible via the browser, or write permission in a remote document storage unit accessible via the browser.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 1, 2013
    Assignee: Google Inc.
    Inventors: Glenn Wilson, Sumit Gwalani, William A. Drewry, Mattias Stefan Nissler, Daniel Kenneth Clifford, Christopher Masone
  • Patent number: 8343827
    Abstract: In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: January 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Yamaguchi, Keiichiro Kashihara, Yoji Kawasaki
  • Patent number: 8344423
    Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Uemoto, Masahiro Hikita, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
  • Patent number: D673808
    Type: Grant
    Filed: March 10, 2012
    Date of Patent: January 8, 2013
    Assignee: WKI Holding Company, Inc.
    Inventors: Steven Grider, Karl Ludeman, Tania Aldous, Dan Streng