Patents Represented by Attorney McGinn IP Law Group, PLLC
  • Patent number: 8351172
    Abstract: A power supply control apparatus includes an output transistor coupled between a first power supply line and an output terminal, the output terminal being configured to be coupled with a load, a discharge transistor coupled between a gate of the output transistor and the output terminal, and rendered conductive when the output transistor is brought into a non-conduction state, a negative voltage control unit coupled between the first power supply line and the gate of the output transistor, and bringing the output transistor into a conduction state when the counter electromotive voltage applied to the output terminal from the load exceeds a predetermined value, a diode having a cathode coupled with the first power supply line, and an anode, a third resistor provided between the anode of the diode and a second power supply line, and a compensation transistor coupled between the second power supply line and the output terminal.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Akihiro Nakahara
  • Patent number: 8349079
    Abstract: An apparatus for manufacturing a Group III nitride semiconductor is composed of a pressure vessel, a reaction vessel disposed within the pressure vessel, a heating device disposed within the pressure vessel so as to heat the reaction vessel, and a glove box filled with argon gas. The pressure vessel and the glove box are connected to each other via a gate valve. By virtue of this configuration, a large-sized reusable reaction vessel can be disposed within the pressure vessel without causing oxidation of Na.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: January 8, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Shiro Yamazaki, Koji Hirata
  • Patent number: 8348438
    Abstract: An object of the present invention is to provide illumination optics that enables improvement in brightness and reestablishment of an irradiation state which is provided with illumination light and which corresponds with a display area, and is to provide illumination optics including a first fly-eye lens and a second fly-eye lens where emission light from the first fly-eye lens enter, wherein at least one of lens elements configuring the second fly-eye lens covers an irradiation area smaller than an irradiation area provided by the second fly-eye lens.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: January 8, 2013
    Assignee: NEC Display Solutions, Ltd.
    Inventors: Masami Takauchi, Masahiko Nishihara
  • Patent number: 8349087
    Abstract: A semiconductor device manufacturing method includes loading plural dry-etched wafers one by one in a container having a side door so as to be disposed substantially horizontally and in layers vertically therein; and blowing out a purge gas horizontally to those wafers loaded in the container for 30 sec or more after all the subject wafers are loaded in the container while the side door is open.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hidetaka Nambu, Nobuo Hironaga, Futoshi Ota, Toru Yokoyama, Osamu Sugawara, Ryo Satou, Masato Tamura
  • Patent number: 8350284
    Abstract: A light emitting element which emits light of a wavelength, includes a substrate which is transparent to the wavelength of emitted light and includes a first surface and a second surface; a semiconductor layer stacked on the first surface; a first electrode which is reflective to the wavelength of emitted light and formed on a surface of the semiconductor layer, wherein electrical resistance of the first electrode in a farthest distance is equal to or smaller than 1?; and a second electrode which is reflective to the wavelength of emitted light and formed on the second surface, wherein electrical resistance of the second electrode in a farthest distance is equal to or smaller than 1?.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: January 8, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Miki Moriyama, Koichi Goshonoo
  • Patent number: 8350842
    Abstract: Designing of a coping for proper working is made possible. Based on three-dimensional data on a model of an abutment tooth to which a dental prosthesis is applied stored in RAM (Random Access Memory) and on three-dimensional position information about a margin line of the model stored in another RAM, on a face containing a reference axis of the model, three-dimensional position information about a side face of a coping is determined so that a specified angle is formed between a margin line and a surface of the model and three-dimensional position information about the side face of the coping on each of a plurality of different faces containing the reference axis over an entire circumference in a direction surrounding the reference axis is detected by a coping processing section.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: January 8, 2013
    Assignee: GC Corporation
    Inventors: Tsutomu Shibata, Yoshinori Matsuda
  • Patent number: 8349142
    Abstract: A graphene production apparatus 100 has a vessel 10 and, attached thereto, an immersion electrode 20 and a non-immersion electrode 30. The immersion electrode has an electrode covering 20c and an electrode main body 20e, and the non-immersion electrode has a covering 30c and an electrode main body 30e. An argon-feeding conduit 40 is disposed so as to inject argon into the vessel 10 around the electrode main body 30e. Ethanol is supplied in such an amount that the liquid surface completely covers the electrode main body 20e of the immersion electrode 20 and does not reach the electrode main body 30e of the non-immersion electrode 30. The electrode main body 20e is formed from, for example, iron, nickel, or cobalt.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 8, 2013
    Assignees: Nu Eco Engineering Co., Ltd.
    Inventors: Masaru Hori, Hiroyuki Kano
  • Patent number: 8351523
    Abstract: A radio communication device for receiving a single-carrier signal transmitted in a partial spectrum of Nyquist frequency band, includes: an interference eliminator for eliminating interference from a received signal by spectrum reproduction of non-transmitted spectra using a symbol replica, to output an interference eliminated signal, wherein the interference includes intersymbol interference which is caused by symbols which are more than a predetermined distance away from a decision symbol point; a symbol sequence estimator for estimating a transmission symbol sequence by separating nearby intersymbol interference within the predetermined distance of the decision symbol point based on the interference eliminated signal, to output a decision signal; and a replica generator for generating the symbol replica from decoding result of the decision signal, wherein the symbol replica is fed back to the frequency-domain interference eliminator.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 8, 2013
    Assignee: NEC Corporation
    Inventors: Yasunori Futatsugi, Shousei Yoshida
  • Patent number: 8351292
    Abstract: A semiconductor device includes: first transmission wirings each transmitting a small-amplitude signal between one of a plurality of first drivers and one of a plurality of receivers; a second transmission wiring transmitting a reference signal connected to each of the plurality of receivers; and a second driver outputting the reference signal with an impedance higher than an impedance with which each of the first drivers outputs the small-amplitude signal. The second transmission wiring is arranged between first and second power supply wirings corresponding to first and second potentials of the small-amplitude signal. The first and second potentials are supplied to each of the first drivers. The plurality of first transmission wirings are arranged close to each other, without being sandwiched between the first and second power supply wirings.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Tatsuya Matano
  • Patent number: 8350389
    Abstract: A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: January 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
  • Patent number: 8348771
    Abstract: A cross shaft member has four shaft portions arranged in a generally cross-shape around an outer periphery of a body portion thereof, and a recessed portion is formed in the body portion, and has a depth in a direction perpendicular to a plane in which axes of the four shaft portions lie. Four ridge-like thickened portions are formed in the recessed portion, and are equally spaced from one another, and extend diagonally with respect to the axes of the shaft portions in the plane.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: January 8, 2013
    Assignee: JTEKT Corporation
    Inventor: Koichiro Mizuno
  • Patent number: 8350323
    Abstract: A semiconductor device may include, but is not limited to: a semiconductor substrate; a bit line; and a contact portion. The semiconductor substrate has a first groove having at least first and second side surfaces facing each other. The bit line is positioned in the first groove. The bit line is insulated from the semiconductor substrate. The contact portion is positioned in the first groove. The contact portion is electrically connected to the bit line. The contact portion contacts the first side surface of the first groove. The contact portion is insulated from the second side surface of the first groove.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: January 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Noriaki Mikasa
  • Patent number: 8351039
    Abstract: A spectroscopy method, includes guiding pulse laser light to an optical fiber, which mutually reacts with a sample to be measured of a light absorptance characteristic, outputting ring down pulse light obtained through light absorption of the sample, measuring an absorptance characteristic of the sample based on an attenuation characteristic of the ring down pulse light, and setting the pulse laser light as wide-spectrum laser light, setting the optical fiber as a strong dispersive optical fiber, and increasing a pulse width of the ring down pulse light to measure a wavelength absorptance characteristic based on a ring down attenuation constant of a pulse train with respect to a time sequence corresponding to a wavelength.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: January 8, 2013
    Assignee: Nu Eco Engineering Co., Ltd.
    Inventors: Masafumi Ito, Norihiko Nishizawa, Masaru Hori, Toshio Goto, Hiroyuki Kano
  • Patent number: 8350357
    Abstract: A first inductor is connected to a transmission circuit. A second inductor is connected to a reception circuit, and is inductively coupled to the first inductor. At least part of the first inductor is formed with a first bonding wire. The first bonding wire has two ends connected to a first connecting terminal and a third connecting terminal. At least part of the second inductor is formed with a second bonding wire. The second bonding wire has two ends connected to a second connecting terminal and a fourth connecting terminal.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masayuki Furumiya, Yasutaka Nakashiba
  • Patent number: 8352150
    Abstract: A storage unit provided in an engine control device stores three kinds of mode maps having different engine output characteristics. One of the mode maps is selected in accordance with the driving conditions, and a target torque is set by referring to the selected mode map using an engine speed and an accelerator opening-degree as parameters. A throttle opening-degree signal corresponding to the target torque is output to a throttle actuator, and an operation of opening or closing the throttle valve is performed in response to the throttle opening-degree signal.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: January 8, 2013
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Kenji Hijikata
  • Patent number: 8344354
    Abstract: A spin-polarized electron generating device includes a substrate, a buffer layer, a strained superlattice layer formed on the buffer layer, and an intermediate layer formed of a crystal having a lattice constant greater than a lattice constant of a crystal of the buffer layer, the intermediate layer intervening between the substrate and the buffer layer. The buffer layer includes cracks formed in a direction perpendicular to the substrate by tensile strain.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: January 1, 2013
    Assignee: National University Corporation Nagoya University
    Inventors: Toru Ujihara, Xiuguang Jin, Yoshikazu Takeda, Tsutomu Nakanishi, Naoto Yamamoto, Takashi Saka, Toshihiro Kato
  • Patent number: 8344269
    Abstract: A semiconductor device includes a substrate, a first pad, a second pad, and a third pad that are placed along one side of a perimeter of the substrate, a circuit that is formed above the substrate, and that is coupled to the first pad, a first external terminal that is coupled to the second pad, and a second external terminal that is coupled to the third pad, wherein the circuit generates a signal indicative of a connection configuration between the first pad and the first external terminal, wherein the third pad is placed adjacent to one of the first pad and the second pad, wherein, in a direction parallel to the one side of the perimeter of the substrate, the first pad, the second pad and the third pad have a first width, a second width and a third width, respectively, and wherein each of the first width of the first pad and the second width of the second pad is smaller than the third width of the third pad.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: January 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyoshi Fukuda
  • Patent number: 8345214
    Abstract: A cooling device is provided that can thin a boundary layer and thus obtain the effect of sufficiently improving the heat transfer coefficient. The cooling device for an electronic apparatus that has a plurality of members juxtaposed such that the surfaces of the members confront each other, the surface of at least one member of these members having a heat discharge surface from which heat is discharged, includes: a duct (100) equipped with an opening (100a) whereby a first air flow emitted from the opening (100a) flows in a first direction along the heat discharge surface, and a duct (101) equipped with an opening (101a) whereby a second airflow emitted from the opening (101a) flows along the heat discharge surface in a second direction that intersects with the first direction. Taking as a boundary a line (200c) that passes through the center (200a) of the heat discharge surface, the center of the opening (101a) is located on the side opposite the side in which the opening (100a) is provided.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: January 1, 2013
    Assignee: NEC Display Solutions, Ltd.
    Inventor: Eisuke Yamashita
  • Patent number: 8343832
    Abstract: A method of forming a semiconductor device includes the following processes. A first pillar and a second pillar are formed on a semiconductor substrate. A semiconductor film is formed which includes first and second portions. The first portion is disposed over a side surface of the first pillar. The second portion is disposed over a side surface of the second pillar. The first and second portions are different from each other in at least one of impurity conductivity type and impurity concentration. A part of the semiconductor film is removed by etching back. The first and second portions are etched at first and second etching rates that are different from each other.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 1, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiro Nishi, Eiichirou Kakehashi
  • Patent number: 8344773
    Abstract: A semiconductor device includes a delay circuit supplied with a first clock signal and a first phase determination signal and producing a second clock signal, the delay circuit controlling the second clock signal such that a delay in phase of the second clock signal to the first clock signal is increased when the first phase determination signal takes a first logic level and decreased when the first phase determination signal takes a second logic level, and a phase determining circuit supplied with the first clock signal and a third clock signal, which is produced in response to the second clock signal, and producing a second phase determination signal in response to a difference in phase between the first clock signal and the third clock signal.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: January 1, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kazutaka Miyano