Abstract: An electrographic printing apparatus comprises a rotatable charge bearing member, a rotatable roller assembly which applies a chargeable pre-wetting oil to the surface of the charge bearing member, a charger assembly which applies uniform charge to the surface of the charge bearing member and/or the pre-wetting oil coating, and a light source which discharges selected areas on the charge bearing member and/or the pre-wetting oil to produce a latent electrostatic image thereon. The electrographic printing apparatus further comprises a liquid development system comprising an ink head assembly which applies liquid toner to the charge bearing member thereby developing the latent electrostatic image, and a rotatable transfer member which receives the developed image from the charge bearing member and then transfers it to a substrate such as paper. The electrographic printing apparatus may also be adapted to produce color images on the substrate.

Abstract: A modulation and demodulation scheme for video signals may be used for HDTV signals using VSB-PAM, analog NTSC signals using VSB-AM and digital video signals using QAM. VSB-PAM modulation and demodulation may be performed using in-phase and quadrature baseband filters. By adjusting the filter taps, a single modulator structure may be used for QAM and VSB-PAM modulation. Similarly, a single demodulator structure may be used for QAM and VSB-PAM demodulation. This demodulator may also be used for VSB-AM modulation.

Abstract: A bridging device for hydrodynamic hydraulic couplings (1), more particularly for turbo couplings of variable or constant filling, which couple a prime mover to a machine and whose input shaft (5) can be coupled by means of the bridging device (D), having a force-transmitting device (11), to its output shaft (8) to increase efficiency of transmission. The force-transmitting device (11) of the bridging device (D) is uncoupled from the rotary motion of the hydraulic coupling (1) and can be controlled by means of a control device disposed outside the casing (2), the bridging device being controllable by means of a fluid.

Abstract: The present invention relates to a method and apparatus in which a differentially coded signal having forward error correction added to the encoded data can be decoded with an improved bit error rate performanceApparatus for decoding a differentially encoded input signal having forward error correction added to the encoded data, the apparatus comprising: a differential decoder to receive the input signal and to decode the data in each differentially encoded signal interval thereof by reference to the data in a previous differentially encoded signal interval; error correcting means to correct errors in the decoded signal form the decoder; and means for supplying to the decoder the corrected data from each signal interval to act as a reference for decoding the data in a following signal interval.

Abstract: A communication method enables a plurality of remote locations to transmit data to a central location. The remote locations simultaneously share a channel and there is a high degree of immunity to channel impairments. At each remote location, data to be transmitted is coded by translating each group of one or more bits of the data into a transform coefficient associated with a frequency in a particular subset of orthonormal baseband frequencies allocated to each remote location. The particular subset of orthonormal baseband frequencies allocated to each location is chosen from a set of orthonormal baseband frequencies. At each remote location, an electronic processor performs an inverse orthogonal transform (e.g., an inverse Fourier Transform) on the transform coefficients to obtain a block of time domain data. The time domain data is then modulated on a carrier for transmission to the central location.

Abstract: A latch circuit has an enable circuit responds to clock pulse levels of a first polarity by outputting an enabling voltage of a second polarity opposite to the first polarity. The latch circuit also has first and second inverters which each have an output, a first biasing input connected to a first polarity voltage, a first input, a second a biasing input receiving the enabling voltage from the enable circuit and a second input. When enabled by the enabling voltage, each inverter drives its respective output to a voltage of the first polarity in response to receiving a signal of the second polarity at its first input. Alternatively, when enabled, each inverter drives its respective output to a voltage of the second polarity in response to receiving a signal of the first polarity at its second input. The first input of the first inverter receives, between the leading and trailing edges of the first polarity clock pulse levels, a signal to be stored.

Abstract: A system and process are provided for controlling congestion at a node of an asynchronous transfer mode (ATM) communications network. The process and system utilize fuzzy logic in determining whether or not to "admit," i.e., allocate a virtual channel (VC) for, new communications (or calls) to the node. Fuzzy logic is also use to control the rate cells are transmitted to the node for communications already "admitted," i.e., for which a VC has already been allocated. The fuzzy logic rules for bandwidth estimation in admission control may be developed from an "equivalent capacity" model. The fuzzy logic rules for adjusting cell transmission rates may be developed from a "two-threshold" congestion control model.

Abstract: A variable length coder is disclosed having a zig-zag memory for continuously receiving blocks of coefficients while outputting the coefficients in zig-zag scan order. The zig-zag memory has a first memory for writing each odd ordinalled block therein according to a zig-zag scan as the odd ordinalled block is inputted. The first memory subsequently reads-out each of the zig-zag scanned odd ordinalled blocks while the zig-zag memory receives each even ordinalled block. The zig-zag memory also has a second memory for writing each even ordinalled block therein according to a zig-zag scan as the even ordinalled block is inputted. The second memory subsequently reads-out each of the zig-zag scanned ordinalled blocks while the zig-zag memory receives each odd ordinalled block. The zig-zag memory further includes a read counter which generates addresses and selectively outputs the addresses to the first memory for reading out each odd ordinalled block, while the zig-zag memory receives an even ordinalled block.

Abstract: A bidirectional buffer circuit is provided with a terminal, an input buffer, a steady state output driver and a strong output driver. The input buffer is for receiving an input signal from the terminal. The steady state output driver includes a weak driver for driving the terminal to a first voltage corresponding to a first particular logic value of the output signal. The weak driver has a limited driving capacity that can be out-driven by the input signal. The strong output driver is for driving the terminal to the first voltage. The strong output driver has a greater driving capacity than the weak output driver. Enable circuitry is also provided. The enable circuitry includes at least one delay circuit with a particular delay period. The enable circuitry enables the strong output driver in response to a transition of the output signal from a complement of the first logic value to the first logic value. However, the enable circuitry only enables the strong driver during the delay period of the delay element.

Abstract: An improved picture hanger has a plate, a screw, and a moveable adjusting hook. The plate comprises a set of upwardly directed wire supports, and a top and a bottom screw support. The screw extends through the top and bottom screw supports. The adjusting hook has a threaded opening which meshes with the threads. This allows the hook to move up and down along the screw when the screw rotates. This picture hanger may include openings or supports to affix a picture light or a safety wire. The plate is affixed to a desired location on a wall. This location need not be precisely measured for height. A support wire is placed in open portions upwardly directed wire supports. The wire is also placed in an open portion of the downwardly directed adjusting hook. This places the wire into an "M" shape after the picture hanging device is affixed to the wall. If the object to be hung is not at the desired height, the height may be adjusted by turning the screw, which raises or lowers the object.

Abstract: A fuzzy reasoning system separately manages fuzzy rule groups, and fuzzy sets each including a plurality of membership functions. When executing fuzzy reasoning, the system selects one fuzzy rule group and at least one fuzzy set in conformity with a situation at that time and combines them. Thereafter, it executes the reasoning for fact information. This arrangement facilitates the building of a flexible fuzzy reasoning system which can confirm to varying situations. In another aspect, the separate management of the fuzzy rule groups and the fuzzy sets allows the selection of only any desired membership function of the fuzzy set to obtain a grade of membership based on the fact information.

Abstract: This and other objects are provided in a method for displaying and managing a set of related images. The invention includes design of screen area in terms of how many, how big, and where workspaces are located. The invention assigns image sets to different workspaces; creates a tree of workspace setups for a specific image viewing session; and allows customization of the tree on a per user, per workstation type basis.

Abstract: A system and process for performing character recognition is disclosed wherein inputted characters are compared to prototypes maintained in a predetermined database of the system to determine the best matching character. To generate the prototype database for use in recognition, training character samples are inputted and classified and prototypes, having feature value vectors, are generated for each class. The prototypes are optimized to improve the recognition capabilities of the database. The prototype feature value vectors are updated by only small amounts for abnormal prototypes that are much closer to the nearest class M than to the true class I. In addition, the updating of the prototype feature value vectors is performed so as to minimize an error in the selection of the prototypes.

Abstract: A method and apparatus for performing multi-stage motion estimation on an input video sequence to be encoded. An original image in the video sequence, such as a CCIR601 image, is preprocessed to generate first, second and third reduced resolution images which may be a QQSIF image, a QSIF image and a SIF image, respectively, which are 1/64 size, 1/16 size and 1/4 size, respectively, relative to the original CCIR601 image. A first stage motion vector search is performed on the 1/64 size QQSIF image using a (0,0) motion vector starting point and a first search range suitable for detecting global motion. A second stage motion vector search is performed on the 1/16 size QSIF image using the (0,0) starting point and a second search range smaller than the first search range and suitable for detecting local motion.

Abstract: The present invention provides a method for achieving alignment of the header fields of a specific layer, such as the transport layer header fields, at a receiving host. The receiving host determines a number of padding bytes that need to be added to the transport layer header for the fields to be properly aligned in the memory of the receiving host. This number is determined dynamically for each connection because different connections require different numbers of padding bytes. The number of padding bytes for a connection is determined by the receiving host from the first packet received for a particular connection. Specifically, the receiving host examines this first packet and determines the position of the first byte of the transport layer protocol header, and therefore, the number of padding bytes required to achieve 32-bit (or 64 bit) alignment. The receiving host communicates the number of padding bytes to the transmitting host.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the invention relates to rate control with panic mode.

Abstract: A method is disclosed for interfacing a video storage system, such as a disk array, and a video stream application executing on a computer network or stand-alone system. The interface provides a method for storing video stream data by allocating storage space in units of stripes and for accessing the data in units of fixed length segments, wherein each stripe includes one fixed length segment from each disk of the array. The interface also queues submitted I/O transaction requests so that I/O transactions requested on a current I/O cycle i are not performed until the next I/O cycle i+1. The I/O transactions thus queued are performed in an order which permits a maximum number of I/O transactions to be performed each I/O cycle, regardless of the order in which they were submitted. In addition, the interface also queues the submitted I/O transaction requests so that the completion of an I/O transaction on a current I/O cycle i is not returned until the next I/O cycle i+1.

Abstract: A circuit for implementing a neural network comprises a one dimensional systolic array of processing elements controlled by a microprocessor. The one dimensional systolic array can implement weighted sum and radial based type networks including neurons with a variety of different activation functions. Pipelined processing and partitioning is used to optimize data flows in the systolic array. Accordingly, the inventive circuit can implement a variety of neural networks in a very efficient manner.

Abstract: A computer system is disclosed which has a master, such as a processor, a memory, and I/O device, a first transfer path, which includes a bus, and a second transfer path, which includes a transfer interconnection. Transfers between the memory and the I/O device are effected via the first path while transfers between the processor and the I/O device are transferred via the second path. The disparate treatment between these two types of transfers reduces the likelihood that the transfer via the second path is delayed and thereby reduces the likelihood that the master is totally blocked from operation.