Abstract: A process for forming a semiconductor structure includes forming a gate dielectric overlying a substrate, a conductive gate electrode overlying the gate dielectric, a barrier layer overlying and in physical contact with the conductive gate electrode, and an organic anti-reflective coating (ARC) layer overlying and in physical contact with the barrier layer.

Abstract: A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that an aspect ratio of the depth to width is greater than one. The semiconductor device further includes a first material having a first portion and a second portion, the first portion of the first material filling the first portion of the at least one opening. Defects for relaxing strain at an interface between the first material and the substrate material exist only within the first portion of the first material due to the aspect ratio being greater than one. The second portion of the first material is substantially defect free. Furthermore, the second portion of the first material and an overlying second material different than the first material fill the overlying second portion of the at least one opening.

Abstract: Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.

Abstract: A system for polishing a substrate has a controller, pressure source, a platen, and a carrier for handling the substrate. The carrier must be able to detect if a substrate is present. In either the case of a false detection of substrate presence or the failure to detect substrate presence, the likely result is damaged substrates, wasted polishing consumables, and down time of the manufacturing facility. Detection is achieved by the substrate causing movement of a plunger and by such movement resulting in a pressure differential that is detected. The reliability of this detection is improved by one or more of a precise relationship of the plunger to a plate that applies pressure to the substrate, a controlled seal that is ensured of being broken when the plunger is moved by the presence of a substrate, and proper spring pressure applied to the plunger to prevent spurious plunger movement.

Abstract: A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness.

Abstract: A method of generating a design of a reticle for a photolithography process. The reticle may include phase shift features, binary features, and mixed features. The method includes generating a reticle design from a pattern layout and then optimizing the reticle design. In some examples, generating the reticle design includes binning the features of the layout based on feature width. Examples of optimization operations include an over/under operation, an under/over operation, a feature segment expansion operation, a feature edge portion conversation from a binary portion to a phase shift portion, a corner binary segment expansion, a discontinuity removal operation, and a feature dimension change operation that includes a determination of a Mask Error Factor (MEF).

Abstract: A method of discharging a charge storage location of a transistor of a non-volatile memory includes applying first and second voltages to a control gate and a well region, respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate of the transistor. The transistor includes a charge storage location having nanoclusters disposed within dielectric material of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

Abstract: A passive integrated component (10) is formed overlying a semiconductor substrate by etching a composite conductive layer using a solution of sodium persulfate or ceric ammonium nitrate to remove a lower portion of the composite copper layer (64) exposed by an upper portion of the composite copper layer (74, 76, 78) to expose an underlying surface (62).

Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Abstract: In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy (414) is formed over a semiconductor bond pad (128), wherein the underbump metallurgy (414) comprises a chromium, copper, and nickel phased-region (404), and wherein the presence of nickel in the phased-region (404) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu6Sn5 copper-tin intermetallics.

Abstract: The present invention relates to a method of determining a thickness of at least one layer on at least one semiconductor wafer (12), comprising the steps of: projecting a first laser pulse (14) on a surface (16) of the at least one layer (10), thereby generating an acoustical wave due to heating of the surface of the at least one layer (10); after a propagation time of the acoustical wave, projecting a series of second laser pulses (18) on the surface (16) of the at least one layer (10); measuring reflected laser pulses (20) of the second laser pulses (18), thereby sensing the times of reflection property changes of the surface (16) of the at least one layer (10); and determining the thickness of the at least one layer (10) by analyzing the times of reflection property changes. The present invention further relates to a system for determining a thickness of a layer (10) on a semiconductor wafer (12).

Abstract: An integrated circuit adapted to output a bandgap reference voltage with temperature coefficient compensation (VBG_TC) includes a first circuit responsive to a bandgap reference voltage (VBG) for generating a temperature stable reference current. A second circuit applies the temperature stable reference current through a current mirror to a current summing junction. A third circuit sums the temperature stable reference current against a current proportional to absolute temperature (IPTAT). Lastly, a fourth circuit converts the summed current into the bandgap reference voltage with temperature coefficient compensation (VBG_TC).

Abstract: A system and method of manufacturing of computing devices. The system and method advantageously provide a work cell and process for physically consolidating the transformation process of a computer system (motherboard prep, chassis prep, assembly, EMR, burn, test and boxing) during manufacturing of the same in one work area. The new consolidating manufacturing assembly work cell provides a streamlined process, automation, furniture, fixtures and intelligent controls which physically consolidate the steps of the transformation process. The work cell includes a new combination of equipment for: (1) Material Handling, (2) performing the assembly steps, (3) detecting and repairing electrical and mechanical problems, and (4) performing burn and test. Further, the integration of the transformation process into one consolidated work cell for the manufacture of computer systems enables a new and more versatile manufacturing process.

Abstract: A build-to-order manufacturing method for producing a custom configured computer system includes obtaining a customer order. Hardware for the custom configured computer system is assembled in accordance with the customer order. The assembled hardware is then tested using software tools and utilities. Next, software is downloaded to the computer system in accordance with the customer order, the software including an operating system (OS). Lastly, a fully integrated system test is performed, the fully integrated system test including the execution of an OS setup for fully integrating the hardware and software of the custom configured computer system and testing of the fully integrated hardware and software from the OS' perspective prior to shipment to a customer.

Abstract: In a method for reduction of data noise in installation packages for a computer system, a first change list is established based upon a set of differences resulting from installation of a configuration change or a vendor product on a first computer system. A second change list is established based upon a set of differences resulting from installation of the configuration change or the vendor product on a second computer system. The first change list is compared with the second change list to produce a resultant change list including an intersecting set of changes. The intersecting set includes common changes between installations on the first computer system and the second computer system, accordingly filtering out of randomly generated installation noise. A re-engineered installation package is created using the intersecting set of changes.

Abstract: A computer system having capability for restoration of a hard disk drive includes at least one processor and at least one hard disk drive. A software image is stored on the at least one hard disk drive, the software image including a factory downloaded image which is subject to corruption. A protected software restoration image not prone to a typical corruption is stored on the at least one hard disk drive and available for use by the at least one processor in executing the restoration of the software image on the at by least one hard disk drive to a like new factory downloaded image condition.

Abstract: A system of manufacturing of computing devices. The system and method advantageously provide a work cell and process for physically consolidating the transformation process of a computer system (motherboard prep, chassis prep, assembly, EMR, burn, test and boxing) during manufacturing of the same in one work area. The new consolidating manufacturing assembly work cell provides a streamlined process, automation, furniture, fixtures and intelligent controls which physically consolidate the steps of the transformation process. The work cell includes a new combination of equipment for: (1) Material Handling, (2) performing the assembly steps, (3) detecting and repairing electrical and mechanical problems, and (4) performing burn and test. Further, the integration of the transformation process into one consolidated work cell for the manufacture of computer systems enables a new and more versatile manufacturing process.

Abstract: A computer system having network controlled security administered in conjunction with a prescribed network server of a computer network includes at least one processor, at least one memory, and a device for communicating with the prescribed network server. Operating system software is provided for use in booting up an operating system. The computer system further includes basic input output system (BIOS) firmware, the BIOS having a security measure. The security measure is implemented by the processor prior to a booting up of the operating system and in conjunction with the prescribed network server. Booting up of the operating system by the processor is controlled in response to the security measure.

Abstract: A method of assaying work of an earth boring bit of a given size and design comprises the steps of drilling a hole with the bit from an initial point to a terminal point. A plurality of electrical incremental actual force signals are generated, each corresponding to a force of the bit over a respective increment of the distance between the initial and terminal points. A plurality of electrical incremental distance signals are also generated, each corresponding to the length of the increment for a respective one of the incremental actual force signals. The incremental actual force signals and the incremental distance signals are processed to produce a value corresponding to the total work done by the bit in drilling from the initial point to the terminal point. Using such a basic work assay, a number of other downhole occurrences and/or conditions can be assayed.

Abstract: A method and apparatus for generating a polyatomic form of a prescribed element is disclosed. The apparatus includes a chamber and a plasma source. The plasma source is coupled to the chamber for producing plasma of the prescribed element from a supply of the element in a gaseous state. The plasma includes at least a mixture of single atomic and double atomic species of the prescribed element. Lastly, a quencher is disposed within the chamber proximate an output of the plasma source for facilitating generation of the polyatomic form of the prescribed element from the mixture of single atomic and double atomic species of the prescribed element. In one embodiment, the element is oxygen and the polyatomic form is ozone.