Abstract: Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.

Abstract: Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of through-silicon vias (TSVs) within a first plane thereof adapted to serve as power, ground and signal interconnections throughout the first plane such that the TSVs that serve as the power and ground interconnections are greater in number and/or size than the TSVs that serve as the signal interconnections; and a plurality of lines within a second plane of the interposer in contact with one or more of the TSVs in the first plane, the second plane being adjacent to the first plane, adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and the ground interconnections are greater in number and/or size than the lines that serve as the signal interconnections.

Abstract: Techniques for content management in wireless mobile networks are provided. In one aspect, a method of managing content stored on a plurality of mobile nodes in a mobile ad hoc network (MANET) is provided. The method includes the following step. The content is bound to one or more geographical locations such that, at any given time, the content is stored on at least one of the nodes at the geographical location.

Abstract: Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

Abstract: Techniques for modeling a data center are provided. In one aspect, a method for modeling a data center is provided. The method comprises the following steps. Spatially dense three-dimensional thermal distribution and air flow measurements made in the data center using a mobile off-line surveying system are obtained. A temperature and air flow model for the data center is created using the spatially dense three-dimensional thermal distribution and air flow measurements. The temperature and air flow model is used to make thermal distribution and air flow predictions of the data center. The thermal distribution and air flow predictions are compared with the thermal distribution and air flow measurements made using the mobile off-line surveying system to produce a validated model for the data center.

Abstract: FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

Abstract: Techniques for increasing conductivity of graphene films by chemical doping are provided. In one aspect, a method for increasing conductivity of a graphene film includes the following steps. The graphene film is formed from one or more graphene sheets. The graphene sheets are exposed to a solution having a one-electron oxidant configured to dope the graphene sheets to increase a conductivity thereof, thereby increasing the overall conductivity of the film. The graphene film can be formed prior to the graphene sheets being exposed to the one-electron oxidant solution. Alternatively, the graphene sheets can be exposed to the one-electron oxidant solution prior to the graphene film being formed. A method of fabricating a transparent electrode on a photovoltaic device from a graphene film is also provided.

Abstract: Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

Abstract: Techniques for organizing information in a user-interactive system based on user interest are provided. In one aspect, a method for operating a system having a plurality of resources through which a user can navigate is provided. The method includes the following steps. When the user accesses the system, the resources are presented to the user in a particular order. Interests of the user in the resources presented are determined. The interests of the user are compared to interests of other users to find one or more subsets of users to which the user belongs by virtue of having similar interests. Upon one or more subsequent accesses to the system by the user, the order in which the resources are presented to the user is based on interests common to the one or more subsets of users to which the user belongs.

Abstract: Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.

Abstract: Techniques for data center analysis are provided. In one aspect, a method for modeling thermal distributions in a data center is provided. The method includes the following steps. Vertical temperature distribution data is obtained for a plurality of locations throughout the data center. The vertical temperature distribution data for each of the locations is plotted as an s-curve, wherein the vertical temperature distribution data reflects physical conditions at each of the locations which is reflected in a shape of the s-curve. Each of the s-curves is represented with a set of parameters that characterize the shape of the s-curve, wherein the s-curve representations make up a knowledge base model of predefined s-curve types from which thermal distributions and associated physical conditions at the plurality of locations throughout the data center can be analyzed.

Abstract: Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided.

Abstract: Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided.

Abstract: Techniques for using air flow analysis to model thermal zones are provided. In one aspect, a method for modeling thermal zones in a space, e.g., in a data center, includes the following steps. A graphical representation of the space is provided. At least one domain is defined in the space for modeling. A mesh is created in the domain by sub-dividing the domain into a set of discrete sub-domains that interconnect a plurality of nodes. Air flow sources and sinks are identified in the domain. Air flow measurements are obtained from one or more of the air flow sources and sinks. An air flow velocity vector at a center of each sub-domain is determined using the air flow measurements obtained from the air flow sources and sinks. Each velocity vector is traced to one of the air flow sources, wherein a combination of the traces to a given one of the air flow sources represents a thermal zone in the space.

Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

Abstract: Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.

Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

Abstract: Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided.

Abstract: Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths.

Abstract: Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.