Patents Represented by Attorney Michael J. Pollock
  • Patent number: 4568882
    Abstract: An FSK demodulator is disclosed suitable for use in a CMOS IC using switched capacitor circuits. The mark and space filters are each modified to produce sine and cosine outputs. These outputs are rectified separately and the result summed. The summed outputs are passed through low pass filters and applied to a comparator which determines which of the mark and space signals is dominant. The invention substantially reduces the size of the demodulator filter capacitors and improves the demodulation signal to noise ratio.
    Type: Grant
    Filed: October 1, 1984
    Date of Patent: February 4, 1986
    Assignee: National Semiconductor Corporation
    Inventor: Peter S. Single
  • Patent number: 4563595
    Abstract: A CMOS Schmitt trigger circuit responsive to TTL logic levels is disclosed. A supply regulator circuit renders the circuit independent of temperature, supply voltage and device parameters.
    Type: Grant
    Filed: October 27, 1983
    Date of Patent: January 7, 1986
    Assignee: National Semiconductor Corporation
    Inventor: Bidyut K. Bose
  • Patent number: 4560921
    Abstract: A comparator circuit is disclosed wherein the input terminals are provided with a predetermined reference potential. Thus, in the case where only one input is driven the other input is biased at close to the reference. In the application of the circuit it is not necessary to provide an external package pin for reference potential.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: December 24, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Mineo Yamatake
  • Patent number: 4552267
    Abstract: A hermetic ceramic semiconductor package is provided with impact absorbing bumpers by applying a composition of sealing glass loaded with malleable metal particles to the ceramic package. The bumpers are applied to the ceramic parts when they are being coated with sealing glass. When the hermetic package seal is formed the bumpers will form a metal loaded matrix that will absorb impacts and thereby avoid chipping of the ceramic package due to impacts during handling.
    Type: Grant
    Filed: March 11, 1985
    Date of Patent: November 12, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Francis W. Layher
  • Patent number: 4553044
    Abstract: An output stage suitable for monolithic semiconductor IC uses is disclosed. The stage employs a pair conventional NPN output transistors biased and driven with conventional bipolar IC elements. The pull up device, which sources output current for positive or rising inputs, is maintained on for negative signal swings so that it can be used to bias the pull down device which is cut off for positive signal swings.
    Type: Grant
    Filed: May 11, 1983
    Date of Patent: November 12, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Harry J. Bittner
  • Patent number: 4550424
    Abstract: An AM stereo receiver decoder is shown. An AM detector produces the stereo L+R signal and a PM detector produces the L-R signal. The PM detector is created from a conventional FM detector that employs an input limiter driving a balanced multiplier. The limiter also drives a tuned circuit which provides quadrature drive to the multiplier. An integrator connected to the FM detector converts the response to a PM decoder. A large value inductor is simulated to appear across the integrator so as to create a low modulation frequency resonance at a subaudible frequency thereby providing a controlled pilot tone response. The inductor is simulated by the action of a first G.sub.m amplifier driving a capacitor which drives a second G.sub.m amplifier having an output coupled back to the input of the first G.sub.m amplifier. The capacitor is switched by means of a series connected switch that disconnects the capacitor when the AM exceeds a predetermined value.
    Type: Grant
    Filed: February 9, 1984
    Date of Patent: October 29, 1985
    Assignee: National Semiconductor Corporation
    Inventors: Fred T. J. Cheng, Don R. Sauer
  • Patent number: 4546307
    Abstract: A current mirror using NPN transistors is described for use in PN junction isolated monolithic integrated circuits. A preferred embodiment operates at high accuracy over a wide range of output currents. It also operates at a relatively high signal frequency. An application in a charge pump, suitable for use in a digital phase locked loop, is detailed.
    Type: Grant
    Filed: January 3, 1984
    Date of Patent: October 8, 1985
    Assignee: National Semiconductor Corporation
    Inventor: William D. Llewellyn
  • Patent number: 4542399
    Abstract: A Darlington output stage is shown in which the saturation voltage is substantially reduced by the incorporation of a complementary transistor. An IC form of the circuit is shown in detail.
    Type: Grant
    Filed: February 22, 1983
    Date of Patent: September 17, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Dennis M. Monticelli
  • Patent number: 4541077
    Abstract: A compensation arrangement is shown for the diffused column line resistance in an N channel metal gate read only memory. The circuit employs a dummy column which has a transistor at each possible location operated from the same decoder that operates the metal gate rows. A current sense circuit clamps the column pull-up end of the dummy column line and provides a correction signal that is fed to the pull-up devices in the memory columns. A second current sense circuit clamps the dummy column sense amplifier end of the column line and provides a correction signal that can be used to compensate the reference currents in column sense amplifiers using differential current sensing.
    Type: Grant
    Filed: November 12, 1982
    Date of Patent: September 10, 1985
    Assignee: National Semiconductor Corporation
    Inventor: A. Karl Rapp
  • Patent number: 4538146
    Abstract: A circuit that monitors the LED driver output pins on an integrated circuit for quiescent moments and then uses those output pins, only during these moments, to strobe keys on a keyboard for input signals.
    Type: Grant
    Filed: September 17, 1982
    Date of Patent: August 27, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Dennis E. Morris
  • Patent number: 4536945
    Abstract: A process is disclosed for making CMOS transistors in combination with self-aligned fully oxide isolated Schottky clamped bipolar transistors.
    Type: Grant
    Filed: April 17, 1984
    Date of Patent: August 27, 1985
    Assignee: National Semiconductor Corporation
    Inventors: Bruce Gray, Kasivisvanatha Soundaranathan, Franklin D. VanGieson
  • Patent number: 4538246
    Abstract: A static random access memory array cell that is non-volatile because when power fails a floating gate is charged or not charged depending on the information content of the cell. When power is restored, all cells are written to a positive state except those with charged floating gates so that the information content of the array is recreated.
    Type: Grant
    Filed: October 29, 1982
    Date of Patent: August 27, 1985
    Assignee: National Semiconductor Corporation
    Inventors: Samuel T. Wang, Chenming Hu, Ying Shum
  • Patent number: 4537237
    Abstract: Our sectional overhead door is allowed to louver through machine mechanisms we have designed. The door louvers allowing ventilation, natural lighting, privacy, and security. These features can be utilized while the door is in the closed position, still allowing for the door to be raised in its normal manner. The louvering angle can be adjusted and locked by the use of one lever, thus allowing for maximum security while in the locked and louvered position. The bottom section will not louver for the purpose of additional security. Through the use of louvering, the above features can be achieved without changing the outward appearance of the structure.
    Type: Grant
    Filed: December 12, 1983
    Date of Patent: August 27, 1985
    Assignee: Robert E. Reid
    Inventors: Frank J. Sepulveda, Robert R. Silva
  • Patent number: 4535399
    Abstract: A switching circuit is employed to control the flow of energy from a power source to a tuned load. The control is achieved by means of a pulse width control voltage. The load current is sensed and fed to a phase locked loop which contains an oscillator producing an output that is slightly above load resonance. The phase locked loop forces the circuit to operate at a frequency where the modulating pulses are initiated at the load current zero crossing. The circuit is shown in use in a regulated d-c power supply and in a fluorescent lamp power supply application.
    Type: Grant
    Filed: June 3, 1983
    Date of Patent: August 13, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Tamas S. Szepesi
  • Patent number: 4533839
    Abstract: In a peripheral driver circuit a switching output transistor is operated from digital logic control and is provided with a shut off circuit which turns the output transistor off when its collector supply current exceeds its saturation current. A controlled base drive current is generated in a circuit that includes a scaled reference transistor that is operated at the same current density and the same collector voltage as the output transistor at its rated current. The reference transistor base current is amplified in a circuit having a current gain equal to the scaling between the reference and output transistors. Thus the base current applied to the output transistor is related to the driver rated current which ensures that saturation will occur up to at least the rated current and above which the shut off will be effective.
    Type: Grant
    Filed: January 10, 1983
    Date of Patent: August 6, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Ramanatha V. Balakrishnan
  • Patent number: 4529895
    Abstract: A three state inverter driver is operated so that its output goes to a logic one briefly just prior to going to its high impedance state when commanded by a disable pulse. This characteristic is useful where a plurality of drivers are employed to operate a DRAM element.
    Type: Grant
    Filed: December 23, 1982
    Date of Patent: July 16, 1985
    Assignee: National Semiconductor Corporation
    Inventors: Timothy L. Garverick, Charles P. Carinalli
  • Patent number: 4528463
    Abstract: A digital driver circuit employs an output transistor having an uncommitted collector that can act as a current sink connectable to a peripheral element that is to be controlled. The base of the output transistor is coupled to a driver circuit that controls the output transistor conduction. The driver input is coupled to a pair of cascaded current mirrors which act to switch the driver off and on. An input stage is coupled to control the current mirrors in response to a low current logic signal.
    Type: Grant
    Filed: June 30, 1982
    Date of Patent: July 9, 1985
    Assignee: National Semiconductor Corporation
    Inventor: David Kung
  • Patent number: 4528496
    Abstract: A current mirror provides an output current, for use in an IC, that is a multiple of a reference current input. A high gain negative feedback loop is coupled between the current mirror reference input and the output device. This forces the reference input to operate as a diode and stabilizes the circuit operation so that the output current accurately reflects the reference current independently of the .beta. of the devices.
    Type: Grant
    Filed: June 23, 1983
    Date of Patent: July 9, 1985
    Assignee: National Semiconductor Corporation
    Inventors: Toyojiro Naokawa, Matsuro Koterasawa
  • Patent number: 4528546
    Abstract: A thick film resistor includes a ceramic substrate 10, a pair of spaced apart electrical connections 30 affixed to the substrate 10, a region of electrically resistive material 21 coated onto the ceramic 10 and not in contact with either of the electrical connections 30, the electrically resistive material adapted to be trimmed 25 and 26 along an edge to thereby lower its resistance, and a pair of spaced apart strips of electrically conductive material 12 and 14 formed on the substrate 10 in electrical contact with the resistive material 21 and extending to a respective one of the pair of connectors 30, the strips 12 and 14 being substantially parallel where in contact with resistive material 21 except at ends of the strips 13 and 15 opposite the location to be trimmed 25. The invention places highest electric field concentrations away from the edge to be trimmed.
    Type: Grant
    Filed: May 2, 1983
    Date of Patent: July 9, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Mark A. Paoli
  • Patent number: RE31967
    Abstract: A gang bonding interconnect tape for use in an automatic bonding machine for gang bonding of semiconductive devices is fabricated by depositing a series of electrically insulative support structures, such as rings of epoxy resin, onto a metallic tape, as of copper, there being at least one of said electrically insulative support structures for individual ones of the interconnect lead patterns to be formed in said metallic tape. The side of the metallic tape, opposite to the support structure, is photoetched with a series of interconnect lead patterns with individual ones of said lead patterns being etched in registration with individual ones of said electrically insulative support structures. The individual electrically insulative support structure, preferably in the form of a ring, is located in each of the lead patterns intermediate the central region thereof and the outer region thereof for supporting the individual leads thereof in circumferentially spaced relation.
    Type: Grant
    Filed: May 7, 1979
    Date of Patent: August 13, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Carmen D. Burns