Patents Represented by Attorney Mills & Onello LLP
  • Patent number: 7985347
    Abstract: In a method of forming a pattern and a method of forming a capacitor, an oxide layer pattern having an opening is formed on a substrate. A conductive layer is formed on the oxide layer pattern and the bottom and sidewalls of the opening. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern including a siloxane polymer. The conductive layer on the oxide layer pattern is selectively removed using the buffer layer pattern as an etching mask. A conductive pattern having a cylindrical shape can be formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: July 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Mi Kim, Young-Ho Kim, Myung-Sun Kim, Jae-Ho Kim, Chang-Ho Lee, Seok Han
  • Patent number: 7981784
    Abstract: Isolation regions are formed on a substrate to define an active region. A gate electrode is formed on the active region. A spacer structure is formed on a sidewall of the gate electrode. A gate silicide layer is formed on the gate electrode and a source/drain silicide layer is formed on the active region adjacent to the gate electrode. An upper portion of the gate silicide layer and a portion of the spacer structure are simultaneously removed to form a spacer structure pattern and a gate silicide layer pattern. A stress layer is formed to cover the gate electrode and spacer structure pattern.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: July 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Ki-Chul Kim, Jung-Deog Lee
  • Patent number: 7977257
    Abstract: In a semiconductor device and a method of manufacturing a semiconductor device, a lower electrode is formed on a semiconductor substrate. A first zirconium oxide layer is formed on the lower electrode by performing a first deposition process using a first zirconium source and a first oxidizing gas. A zirconium carbo-oxynitride layer is formed on the first zirconium oxide layer by performing a second deposition process using a second zirconium source, a second oxidizing gas and a nitriding gas, and an upper electrode is formed on the zirconium carbo-oxynitride layer. A zirconium oxide-based composite layer having a high dielectric constant and a thin equivalent oxide thickness can be obtained.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Hong Kim, Min-Woo Song, Pan-Kwi Park, Jung-Min Park
  • Patent number: 7978584
    Abstract: There is provided a method and device for reading, writing, or both, data from or to a pattern recognition type optical memory having a light transmittable substrate. Patterns can be formed in the pattern recognition type optical memory from light images representing the data. An optical memory reading device comprises a light source, an image detecting unit for detecting images corresponding to the patterns and generating image signals converted by an optical/electric converter into electric signals. An optical memory writing device comprises a light source, an electric/optical converter for receiving an electric signal corresponding to the data and converting the electric signal into an image signal, and an image generation unit for receiving the light emitted from the light source and the image signal and generating light images corresponding to the image signal, wherein the images are configured to form the patterns on the light transmittable substrate.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-kyun Tak, Chang-hyun Kim, Yeong-taek Lee, Jae-woong Hyun
  • Patent number: 7977724
    Abstract: A capacitor includes a cylindrical storage electrode formed on a substrate. A ring-shaped stabilizing member encloses an upper portion of the storage electrode to structurally support the storage electrode and an adjacent storage electrode. The ring-shaped stabilizing member is substantially perpendicular to the storage electrode and extends in a direction where the adjacent storage electrode is arranged. A dielectric layer is formed on the storage electrode. A plate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-Min Park
  • Patent number: 7971478
    Abstract: A wind sensor includes first and second elements in an orthogonal axis arrangement and a calibration data array comprising first calibration data associated with the first element and second calibration array data associated with second element. An anemometric processor determines a wind speed (S) and direction (W) for an airflow received by the first and second elements using a first electrical parameter associated with the first element and the first calibration array data and a second electrical parameter associated with the second element and the second calibration array data. A wind sensing probe can have a pair of wind sensing elements, wherein each element has a core formed of a low specific heat, low density, high temperature plastic polymer, with two metal leads extending from the ends of core. A wind sensing element can include a fine Nickel alloy coil wound around an aforementioned core.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: July 5, 2011
    Inventors: Harvey Harrison, Richard Paskowsky
  • Patent number: 7972914
    Abstract: A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-min Kim, Min-sang Kim, Eun-jung Yun
  • Patent number: 7973343
    Abstract: A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Jung Yun, Min-Sang Kim, Sung-Min Kim, Sung-Young Lee, Ji-Myoung Lee, In-Hyuk Choi
  • Patent number: 7968355
    Abstract: The present invention is directed to a vertical-type luminous device and high through-put methods of manufacturing the luminous device. These luminous devices can be utilized in a variety of luminous packages, which can be placed in luminous systems. The luminous devices are designed to maximize light emitting efficiency and/or thermal dissipation. Other improvements include an embedded zener diode to protect against harmful reverse bias voltages.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: YuSik Kim
  • Patent number: 7968442
    Abstract: A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-hoon Kang, Tai-su Park, Dong-chan Kim, Yu-gyun Shin, Jeong-do Ryu, Seong-hoon Jeong
  • Patent number: 7968356
    Abstract: Provided are a light-emitting element, a light-emitting device including the same, and methods of fabricating the light-emitting element and the light-emitting device. The light-emitting element includes a substrate on which a dome pattern is formed and a light-emitting structure conformally formed on the dome pattern. The light-emitting structure includes a first conductive layer of a first conductivity type, a light-emitting layer, and a second conductive layer of a second conductivity type sequentially stacked on the substrate. The light-emitting element also includes a first electrode formed on the first conductive layer and a second electrode formed on the second conductive layer.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yu-Sik Kim
  • Patent number: 7968410
    Abstract: A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ji Jung, Sang-woo Lee, Jeong-gil Lee, Gil-heyun Choi, Chang-won Lee, Byung-hee Kim, Jin-ho Park
  • Patent number: 7968447
    Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Ho Lee, Jae-Hwang Sim, Jae-Kwan Park, Mo-Seok Kim, Jong-Min Lee, Dong-Sik Lee
  • Patent number: 7964454
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Patent number: 7965145
    Abstract: A voltage-controlled oscillator (VCO) circuit includes a level shifter, and a semiconductor device includes the VCO circuit. The VCO circuit includes an input voltage receiver, a current mirror, and a frequency oscillator. The input voltage receiver receives a first voltage input to the VCO circuit so as to generate a first current. The current mirror copies the first current so as to generate a second current. The frequency oscillator oscillates in response to the second current. The input voltage receiver includes a level shifter and a first current generator. The level shifter shifts a voltage level of the first voltage to a voltage level of a second voltage. The first current generator generates the first current corresponding to the second voltage.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-hyun Kim, Jung-hyeon Kim
  • Patent number: 7966446
    Abstract: A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joo-Sun Choi
  • Patent number: 7965910
    Abstract: In a system and method, the emitted beams of multiple diode bar array assemblies are combined to achieve an increase in the resulting power density in the combined output beam, while addressing the need for heat distribution in each of the individual assemblies. The present invention enables the combination of output planes of illumination, to form a single, merged beam of area Ag having intensity IM˜M*Istack and brightness BM˜M*Bstack, where Istack and Bstack refer respectively to the intensity and brightness of the output plane of illumination of a single stacked array, and where IM and BM refer respectively to the intensity and brightness of the combined output plane of illumination of M stacked arrays. In this manner, the present invention is useful in applications where there is a need for high-intensity, high-brightness light energy.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: June 21, 2011
    Assignee: Textron Systems Corporation
    Inventors: Daniel E. Klimek, Alexander E. Mandl
  • Patent number: 7961521
    Abstract: A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first inverting circuit, a second load element, a second inverting circuit, and a sense amplifier. The first load element includes an end connected with a bit line of a main cell array within the flash memory device. The first inverting circuit includes an input terminal connected with the bit line of the main cell array and an output terminal connected with another end of the first load element. The second load element includes an end connected with a bit line of a reference cell array within the flash memory device. The second inverting circuit includes an input terminal connected with the bit line of the reference cell array and an output terminal connected with another end of the second load element.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Se-eun O
  • Patent number: 7960655
    Abstract: A PCB can include an insulating member, a cooling member, and a circuit pattern. The cooling member can be built into the insulating member. The cooling member can have a cooling passageway through which a cooling fluid can flow. The circuit pattern can be formed on the insulating member. Thus, high heat in the circuit pattern can be rapidly dissipated by the cooling fluid flowing through the cooling passageway.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Chan Han, Dong-Chun Lee, Young-Soo Lee
  • Patent number: 7959172
    Abstract: A push-in-bung assembly is provided that improves vibration and lateral movement control for vehicle suspension systems. The push-in-bung assembly includes a bung formed of rigid material and having a first end configured to connect to a vehicle frame and a second end configured to connect to a vehicle differential. A track bar can be included between the bung and the vehicle frame. The track bar can connect with the vehicle frame using a bracket assembly.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: June 14, 2011
    Inventors: Michael Nashawaty, Stephen Nashawaty