Abstract: One non-limiting but advantageous aspect of the present invention relates to improved airport efficiency and capacity through higher utilization of a primary runway. The improvements derive from the use of one or more high-speed exit ramps that interconnect the primary runway to a high-speed landing way running parallel to the primary runway. The high-speed exit ramp(s) enable a landing aircraft to negotiate a high-speed transition from the primary runway to the high-speed landing way, so that the aircraft completes its landing roll out and transition to taxiing speeds on the high-speed landing way rather than the primary runway. In at least one embodiment, a computerized landing controller indicates to pilots of landing aircraft whether their aircraft are permitted to take a high-speed exit ramp via control of an associated high-speed exit lighting system.

Abstract: The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.

Abstract: A first communication device estimates upstream channel conditions for an upstream channel and determines an upstream memory requirement for a first buffer at a second communication device and a first buffer at the first communication device based on the upstream channel conditions. A downstream memory requirement is received from the second communication device for a second buffer at the first communication device and a second buffer at the second communication device based on downstream channel conditions estimated at the second communication device for a downstream channel. The first communication device determines whether the sum of the upstream and downstream memory requirements exceeds an available amount of memory for implementing the first and second buffers at the first communication device and revises at least one of the memory requirements if the sum of the upstream and downstream memory requirements is different than the available amount of memory.

Abstract: A three way wideband Doherty amplifier circuit includes a first peaking amplifier operable to turn on at a first power level, a second peaking amplifier operable to turn on at a second power level below the first power level and a main power amplifier operable to turn on at all power levels. The main power amplifier has a high impedance load modulated state when the first and second peaking amplifiers are turned off. The three way wideband Doherty amplifier circuit further includes a constant impedance combiner connected to an output of each amplifier. The constant impedance combiner has a characteristic impedance which matches the impedance of the main amplifier in the high impedance load modulated state with or without an output matching device connecting the main amplifier output to the constant impedance combiner, as viewed from the output of the main amplifier.

Abstract: A power semiconductor module includes a package having a first package portion and a second package portion. The side of the first package portion facing the second package portion has an anchoring element with a first recess. The second package portion includes a second recess with an indentation which receives the anchoring element. To produce a mechanically firm connection between the first package portion and the second package portion, a plug-in element is inserted in the first recess and the second recess. The plug-in element displaces the anchoring element transversely with respect to the plug-in direction, causing the anchoring element to engage the indentation so that a form-fit connection is produced between the first package portion and the second package portion. The plug-in element prevents the anchoring element from disengaging the indentation.

Abstract: A baseband signal is processed by amplifying a first pulse width modulation radio frequency signal having a first non-negligible peak-to-peak amplitude and a second non-negligible peak-to-peak amplitude larger than the first non-negligible peak-to-peak amplitude. A second pulse width modulation radio frequency signal is also amplified, the second pulse width modulation radio frequency signal having a third non-negligible peak-to-peak amplitude approximately equal to the second non-negligible peak-to-peak amplitude of the first pulse width modulation signal when the baseband signal power is at or above the second threshold level. The amplified signals are constructively combined to form a pulse width modulation radio frequency signal comprising a plurality of non-negligible peak-to-peak amplitude levels each corresponding to a different baseband signal power range.

Abstract: A press-fit connecting element for being pressed into a first contact opening in a first connection element and into a second contact opening in a second connection element is provided. The press-fit connecting element includes an elongated base body configured to be guided through the second contact opening in the second connection element to the first contact opening in the first connection element. The press-fit connecting element further includes a first press-fit zone configured to contact-connect the first contact opening in a force-fitting manner and a second press-fit zone which is at a distance from the first press-fit zone in a longitudinal direction and configured to contact-connect the second contact opening in a force-fitting manner.

Abstract: A method and an apparatus for ultrasonic welding of a first workpiece to a second workpiece is disclosed. The two workpieces are clamped between a sonotrode and an anvil so that the two workpieces are in mechanical contact with each other, the first workpiece is in mechanical contact with the sonotrode and the second workpiece rests on the anvil. Fluid is introduced between the second workpiece and the anvil so that the second workpiece at least partly rests on the fluid. The fluid is frozen so that the fluid forms a solid body. Ultrasonic vibrations are applied to the first workpiece by the sonotrode for a period of time.

Abstract: The invention relates to a power semiconductor module including a power semiconductor chip arranged on a substrate and comprising a bottom side facing the substrate, a top side facing away from the substrate, and an electrical contact face arranged on the top side. A bond wire is bonded to the contact face. At least when the power semiconductor module is fastened to a heatsink, a contact pressure element creates a contact pressure force (F) acting on a sub-portion 36 of a bond wire portion configured between two adjacent bond sites. The contact pressure force (F) results in the power semiconductor chip and a substrate beneath being pressed against the heatsink.

Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.

Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.

Abstract: A method is disclosed of synchronizing a first high data-rate radio transceiver and a second high data-rate radio transceiver. The first high data-rate radio transceiver is associated to a first lower data-rate radio transceiver and the second high data-rate radio transceiver is associated to a second lower data-rate radio transceiver. The method comprises time synchronizing the first and second lower data-rate radio transceivers, determining a timing information concerning operation of the first high data-rate radio transceiver relative to operation of the first lower data-rate radio transceiver, transmitting the timing information to the second lower data-rate radio transceiver, and time synchronizing the first and second high data-rate radio transceivers using the transmitted timing information.

Abstract: The invention relates to a method for fabricating a high-temperature compatible power semiconductor module in which a power semiconductor chip is bonded by means of a diffusion solder layer to a substrate and said substrate is bonded by means of silver sintered layer to a base plate, after which a bonding element is bonded to the top chip metallization. To prevent oxidation of the predefined bond area when producing the diffusion solder layer and the sintered silver layer 4? an anti-oxidation layer is applied to the top chip metallization at least in the region of the predefined bond area.

Abstract: A power circuit includes a power device, an output match network and a bypass network. The output match network is coupled to an output of the power device and includes a blocking capacitor which forms part of a high quality factor RF path of the output match network. The output match network is operable to provide a range of impedance matching over a signal bandwidth and a low frequency gain peak outside the signal bandwidth which corresponds to a low frequency resonance of the high quality factor RF path. The bypass network is coupled in parallel with the blocking capacitor of the output match network. The bypass network is operable to attenuate the low frequency gain peak while maintaining the high quality factor RF path.

Abstract: According to a method and apparatus taught herein, an optical sensor uses pattern recognition in its optical detection processing to “see” detection patterns that correspond to predefined configuration settings. In one embodiment, for example, an optical sensing system selects an operational configuration by detecting a pattern embodied in received light data and comparing the detected pattern to one or more internally stored patterns. Each stored pattern represents a different operational configuration of the optical sensing system. If the detected pattern matches one of the stored patterns, the optical sensing system adopts the operational configuration corresponding to the matched stored pattern. Further, in one or more embodiments, the optical sensing system enters a configuration mode by an external stimulus, e.g., responsive to a configuration mode input, and the aforementioned pattern detection-based configuration selection is enabled only while in the configuration mode.

Abstract: A power semiconductor module is fabricated by providing a circuit substrate with a metal surface and an insulating substrate comprising an insulation carrier featuring a bottom side provided with a bottom metallization layer. An anchoring structure is provided comprising a plurality of oblong pillars each featuring a first end facing away from the insulation carrier, at least a subset of the pillars being distributed over the anchoring structure in its entirety, it applying for each of the pillars of the subset that from a sidewall thereof no or a maximum of three elongated bonding webs each extend to a sidewall of another pillar where they are bonded thereto. The anchoring structure is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom metallization layer and anchoring structure by means of a solder packing all interstices between the metal surface and bottom metallization layer with the solder.

Abstract: A refrigerated truck has a power management system for optimally distributing power between one or more energy sources, energy sinks, or energy storage components on the refrigerated truck. One such power consuming component includes a refrigeration unit that cools a refrigerated compartment of the refrigerated truck. Particularly with regard to this refrigeration unit, the power management system is operative to direct power from multiple power sources to the refrigeration unit so as to efficiently use available power. To do so, the power management system dynamically determines the availability of certain power sources and selects a preferred power source based on availability and a defined order of power source preference.

Abstract: High-definition multimedia interface (HDMI) plugs are modified to include one or more retention features that increase the force needed to extract a fully inserted HDMI plug from a compatible mating receptacle. In several embodiments, a high-definition multimedia interface (HDMI) plug includes a connector body having a mating end configured for insertion in a longitudinal direction into a mating HDMI receptacle and having a slot-shaped opening along at least one wall of the connector body, extending in the longitudinal direction. A movable tab is biased to extend outward from the slot-shaped opening in a first position, when unconstrained by the mating HDMI receptacle, and configured to retreat into a second position, substantially within said opening, when longitudinally engaged by a leading edge of the mating HDMI receptacle during insertion of the connector body. Additional retention features and mating HDMI receptacles are also described.

Abstract: A transistor with a gate electrode structure is produced by providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface. A first trench extending from the first surface into the semiconductor body is formed by removing the sacrificial layer in a section adjacent the first surface. A second trench is formed by isotropically etching the semiconductor body in the first trench. A third trench is formed below the second trench by removing at least a part of the first sacrificial layer below the second trench. A dielectric layer is formed which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench. A gate electrode is formed on the dielectric layer in the second trench. The gate electrode and dielectric layer in the second trench form the gate electrode structure.

Abstract: An input sequence of musical notes is converted to a melodic contour by detecting note interval changes, e.g., in semitones, between consecutive musical notes in the sequence and mapping the detected note interval changes to corresponding change codes in a defined set of change codes, which have non-uniform step sizes for quantizing note interval changes. Correspondingly, a system, such as a local and/or a remote computer system system (e.g., a web-based melody search server) compares input melodic contours with a database of stored melodic contours to determine matching information, which can be provided to the users that generated the input sequences of musical notes. The system may be configured to search computer networks to identify audio files for representation in the database of stored melodic contours. Further, an embodiment provides for a graphical keyboard for entry of musical note sequences and/or provides for receiving such sequences through a MIDI port.