Patents Represented by Attorney Nathan Cass
  • Patent number: 5070477
    Abstract: A port adapter for an input/output system for a large data processing system. The port adapter is coupled to an I/O processor of that system and also to main memory of the system so that when the port adapter is selected by a system interrupt message from the I/O processor, it can begin and carry on its data transmission between a selected peripheral device and main memory without further assistance. The port adapter has two peripheral interface transceivers so that it can concurrently control data transfers to at least two peripheral devices.
    Type: Grant
    Filed: March 23, 1989
    Date of Patent: December 3, 1991
    Assignee: Unisys Coporation
    Inventors: Farrukh A. Latif, Michael D. Stevens
  • Patent number: 5068782
    Abstract: Accessing control means and methods are provided for controlling the granting of access by a plurality of requestors to a commonly shared unit on a predetermined priority basis. An addressable programmed memory, such as a ROM, is programmed to provide a predetermined access priority. The ROM operates in response to sequentially applied addresses to produce ROM outputs which determine the manner in which access is granted to the requestors. Each ROM output also includes history outputs which are fed back and combined with requestor signals to form each ROM address, whereby requestor access grating selection is determined based on previous access granting history as well as on current request status.
    Type: Grant
    Filed: October 5, 1989
    Date of Patent: November 26, 1991
    Assignee: Unisys Corp.
    Inventors: James H. Scheuneman, Lawrence R. Fontaine
  • Patent number: 5064376
    Abstract: A portable compact target motion simulation system, adapted to generate simulated target motion for displaying, tracking, and controlling a plurality of simulated targets on a display device for training purposes. The system is operable to generate pre-programmed and dynamic exercises, for training trainees in operating tracking devices, to develop trainee skill in analyzing and responding properly to target motion.The apparatus is totally programmable, and capable of providing targets in any matrix. It includes a target display generator, adapted to store, merge, and transmit timed data signals for driving a target-display device. It further includes a dynamic target motion generator, microprocessor-based, adapted to receive input data identifying the characteristics of particular operator-controlled targets and convert such data into dynamic target motion input data for driving the target display generator.
    Type: Grant
    Filed: April 1, 1983
    Date of Patent: November 12, 1991
    Assignee: Unisys Corporation
    Inventor: Ronald DeCrescent
  • Patent number: 5034879
    Abstract: A processor is disclosed having two levels of subinstructions, with the processor data bus being selectable as either a 16 bit or 32 bit wide bus under nanoprogram control.
    Type: Grant
    Filed: October 24, 1988
    Date of Patent: July 23, 1991
    Assignee: Unisys Corp. (Formerly Burroughs Corp.)
    Inventors: Thomas R. Woodward, David D. McCoach
  • Patent number: 5027233
    Abstract: Shown is a disk drive arrangement with servo-mechanism for controlling (thin-film) head position, etc.; the servo having a disk face dedicated to servo tracks, rendered in "Quad" code, with special timing indicia to separate position indicia, with position signals being deployed to follow, and to be terminated by, like, distinct timing sequences.
    Type: Grant
    Filed: August 12, 1988
    Date of Patent: June 25, 1991
    Assignee: Unisys Corp.
    Inventors: Eugenio Berti, Ashraf I. El-Sadi
  • Patent number: 5025327
    Abstract: Write precompensation data is recorded on a disk of a magnetic disk drive indicating the write compensation to be provided for each of a plurality of head/media combination which may have relatively wide variations in performance characteristics. Apparatus is provided for transferring and storing this write precompensation data in the disk controller at start-up and for accessing this stored data during each write operation to provide a "tailored" write precompensation for the particular head/media combination to be employed for the writing operation.
    Type: Grant
    Filed: October 17, 1986
    Date of Patent: June 18, 1991
    Assignee: Unisys Corp.
    Inventors: Jesse I. Stamness, Raymond W. Morrow, Edward E. Asato
  • Patent number: 5010641
    Abstract: A method of making a multilayer printed circuit board providing sufficient internal distributed capacitance so as to eliminate the need for the by-pass capacitor conventionally provided in the vicinity of each integrated circuit mounted to the board. The method includes providing one or more fully-cured power-ground plane sandwich components which are laminated together with other partially cured component layers of the board. Each sandwich component comprises a conductive power plane layer and a conductive ground plane layer having a fully cured dielectric material therebetween. The thickness of the dielectric layer of each sandwich is chosen sufficiently thin to provide the desired distributed capacitance.
    Type: Grant
    Filed: June 30, 1989
    Date of Patent: April 30, 1991
    Assignee: Unisys Corp.
    Inventor: John R. Sisler
  • Patent number: 5010482
    Abstract: A mechanism for queuing a set of happened events in order of their occurrence and allowing for multiple occurrences to result in multiple processing iterations which mechanism maintains a multi-event table which is really a table of multi-event designations to be allocated to different processes upon request where the requesting processes assign a particular function with each multi-event entry and each of its own related event designations.
    Type: Grant
    Filed: March 23, 1989
    Date of Patent: April 23, 1991
    Assignee: Unisys Corp.
    Inventors: John A. Keller, Barry S. Traylor, Robert H. Tickner
  • Patent number: 5007010
    Abstract: A fast BCD/Binary Adder in which provision is made for selectively performing either binary or BCD arithmetic operations using an approach in which, for BCD addition, an appropriate correction value is always caused to be added to one of the input operands and an appropriate correction value conditionally subtracted from the result where required to give a proper BCD result. High speed operation is achieved by merging the binary input logic with the correction logic so as to provide for addition of the correction value concurrently with the addition of the input operands in a manner which automatically takes into account any inter-bit carries that may be produced by the correction value. In addition, provision is made for concurrently producing conditional sums (one assuming the presence of an input carry and the other assuming the absence of a carry) in parallel with the performance of look-ahead carry operations.
    Type: Grant
    Filed: March 25, 1986
    Date of Patent: April 9, 1991
    Assignee: Unisys Corp. (Formerly Burroughs Corp.)
    Inventor: Laurence P. Flora
  • Patent number: 5006787
    Abstract: An application specific integrated circuit is provided on a chip where a combinatorial logic circuitry such as a RAM memory array, logic circuitry and control circuitry may be operated in the normal mode with the addition of a built-in, self-test feature whereby the registers can be converted to multifunction shift registers which are connected in a serial fashion to form a shift chain snake through which data patterns can be shifted. Additionally, control circuitry is provided to select certain multifunction shift registers as test pattern generators and other multifunction shift registers are receivers of signatures which can be accessed by a maintenance controller to check proper operability of the system and its combinatorial logic.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: April 9, 1991
    Assignee: Unisys Corporation
    Inventors: Haluk Katircioglu, John A. De Beule, Debaditya Mukherjee
  • Patent number: 4986490
    Abstract: An improved photographic film supply and threading mechanism which enables a person to prepare a document record camera 44,45 for use without having to feed the film 36 through a complex system of guides and rollers 38, 42 within the body of the camera where the lens and shutter system are exposed to possible displacement and damage. The film 36 is simply fed around a pattern of rollers 38, 42 from a supply reel 22 to a take-up reel 26 mounted on a suitable support assembly 10,14. The assembly is then placed into the body of the camera 44,45 where a combination of film tension arms 59,71 and associated motor control switches act 60,72 together to position the film 36 along a path crossing the image plane 44 of the camera where when the assembly is in position as sensed by a switch 74 it may be exposed as the camera control circuit FIG. 4 advances the film.
    Type: Grant
    Filed: January 19, 1989
    Date of Patent: January 22, 1991
    Assignee: Unisys Corp.
    Inventor: Michael N. Tranquilla
  • Patent number: 4984355
    Abstract: A dual purpose tool for inserting and extracting a PGA multi-in package into associated socket on a PC board.
    Type: Grant
    Filed: March 6, 1989
    Date of Patent: January 15, 1991
    Assignee: Unisys Corporation
    Inventors: Rocco V. Lubrano, Ladislaw D. Cubranich
  • Patent number: 4977495
    Abstract: A system for maintaining a cache in the main memory of a large data processing system for storing many tracks of data received from a large number of disk files where the disk files are non-volatile which is required to store critical customer data. More importantly, the present invention resides in a software system which is a part of the operating system of a large data processing system to maintain this cache.
    Type: Grant
    Filed: February 29, 1988
    Date of Patent: December 11, 1990
    Assignee: Unisys Corporation
    Inventors: William Stratton, Carol Wellington
  • Patent number: 4975837
    Abstract: A processor has two levels of subinstructions, each stored in its own memory with the lower level memory containing only a limited set of such lower level instructions with the rest of the lower level instructions that are desired to be used being supplied by the code stream from the upper level memory.
    Type: Grant
    Filed: October 7, 1988
    Date of Patent: December 4, 1990
    Assignee: Unisys Corporation
    Inventors: Thomas R. Woodward, David D. McCoach
  • Patent number: 4970419
    Abstract: Transmission line termination circuitry is provided on a driven IC chip utilizing active transistors constructed and arranged so as to steer appropriately directed damping currents into the input bus in a manner which effectively minimizes both overshoot and undershoot without making undue demands on the normally provided chip power supply.
    Type: Grant
    Filed: March 23, 1987
    Date of Patent: November 13, 1990
    Assignee: Unisys Corporation
    Inventors: Timothy P. Hagen, Paul G. Tumms
  • Patent number: 4958351
    Abstract: A multiplicity of independently operating disk drive subsystems are coupled to a read/write interface containing error circuitry and data organizer circuitry. The data organizer circuitry organizes read/write data for read/write communication with the disk drive subsystems via the error circuitry such that the overall system appears as a large, high capacity disk drive system having an unusually high fault tolerance and a very high bandpass. Caching is additionally provided in the read/write interface in a manner which takes advantage of the organization provided by the data organizer to significantly improve overall performance. Advantage is also taken of the conventionally provided error detection capability of each disk drive subsystem to enhance the capability of the error circuitry.
    Type: Grant
    Filed: April 1, 1988
    Date of Patent: September 18, 1990
    Assignee: Unisys Corp.
    Inventors: Laurence P. Flora, Gary V. Ruby
  • Patent number: 4932028
    Abstract: A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.
    Type: Grant
    Filed: June 21, 1988
    Date of Patent: June 5, 1990
    Assignee: Unisys Corporation
    Inventors: Haluk Katircioglu, John A. De Beule, Debaditya Mukherjee, Gary C. Whitlock
  • Patent number: 4918378
    Abstract: A method for internal self-testing is provided for a VLSI chip having gates, logic, registers, memory circuitry, etc. The registers are connected into a shift chain circuit form. A set of control flip-flops operate to convert the registers to multifunction shift registers (MFSR's) which operate as flip-flops during a test cycle and as latches during normal operations. Selected MFSR's function to generate test patterns to the chip circuitry which have output signals to an output MFSR which collects a signature that can be compared to a predetermined signature to determine error-free or error-incurred operation of the VLSI circuitry.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: April 17, 1990
    Assignee: Unisys Corporation
    Inventors: Haluk Katircioglu, John A. De Beule, Debaditya Mukherjee
  • Patent number: 4915222
    Abstract: A protective package unit for shipping printed circuit boards provides an outer container into which one or more printed circuit boards can cushionably reside while encompassed in a see-through bag providing protection from electromagnetic radiation and electrostatic discharge.
    Type: Grant
    Filed: August 1, 1988
    Date of Patent: April 10, 1990
    Assignees: Unisys Corporation, Conceptual Design Industries
    Inventors: Deborah L. Reidinger, Michael S. Freitas
  • Patent number: D323743
    Type: Grant
    Filed: March 6, 1989
    Date of Patent: February 11, 1992
    Assignee: Unisys Corporation
    Inventors: Vincent DiSessa, Matthew D. Marhefka