Patents Represented by Attorney Nathan Cass
  • Patent number: 4905184
    Abstract: A buffer memory in a peripheral controller has dedicated page and word location segments for each one of a multiple number of attached peripheral units. Additionally, an auxiliary segment provides memory for the active status of each one of the multiple number of data transfer cycle operations which may be occurring concurrently and which status can be accessed at the optimum time so that each initiated data transfer cycle can be completed in a time-saving fashion. Memory address control means are provided for accessing page segments and word locations therein in order to insert data therein or to remove data therefrom. A special queue segment is available to provide concurrent status information for each I/O command initiated by a host computer.
    Type: Grant
    Filed: September 21, 1987
    Date of Patent: February 27, 1990
    Assignee: Unisys Corporation
    Inventors: Rangaswamy P. Giridhar, Jeffrey T. Reeve
  • Patent number: 4897813
    Abstract: A non-reprogrammable ROM holding microinstruction words cooperates with a Content Addressable Memory made of a TAG Memory and Data Memory. Portions of the locations in the TAG Memory have the same address as certain locations in the ROM so that when these selected addresses occur, a multiplexer will select the updated data from the Data Memory rather that from the ROM. The entire system is placed on one chip and provides great spatial surface savings over that which would be required if only a Static RAM were used for a control storage unit to hold the microinstruction words.
    Type: Grant
    Filed: February 19, 1988
    Date of Patent: January 30, 1990
    Assignee: Unisys Corporation
    Inventor: Cevat Kumbasar
  • Patent number: 4888759
    Abstract: An optical memory system is disclosed employing laser beams for reading and writing data in an optical disk. The system incorporates a specially designed spatial combining and separating device which functions to combine a writing laser beam with a plurality of reading laser beams in a manner so as to permit the combined beams to be precisely focused on the disk. The spatial combining and separating device also functions to separate the reading laser beams from the writing laser beam after they are reflected from the disk in a manner so as to prevent the higher intensity writing beam from interfering with the proper detection of the lower intensity reading beams.
    Type: Grant
    Filed: September 9, 1982
    Date of Patent: December 19, 1989
    Assignee: Burroughs Corporation
    Inventors: Robert L. Hazel, Gilbert Y. H. Chan
  • Patent number: 4885683
    Abstract: A data link processor (peripheral-controller), for managing data transfers to/from multiple disk drive modules, provides a hardware self-test operation to its subsystem card units when it is powered on. The data link processor momentarily disables its interfaces to the peripheral disk drives and the host computer to execute test operations and to indicate either the integrity condition or fault condition of its card units. Each card unit also has a pushbutton for self-test initiation and a local light-emitting diode which lights up and stays lit up if the card unit is misfunctioning to indicate a failed card unit. Further, the connected host computer can initiate the self-test operation for the peripheral-controller for integrity testing.
    Type: Grant
    Filed: September 12, 1988
    Date of Patent: December 5, 1989
    Assignee: Unisys Corporation
    Inventor: Ronald S. Coogan
  • Patent number: 4868734
    Abstract: An improved input/output subsystem allowing data transfers between the input/output subsystem and an input/output controller along a subsystem input/output bus to occur at a data transfer rate established by the transfer rate of the processor bus connected between the input/output controller and the central processing unit. Data is transferred from an electronic memory within the input/output subsystem to data buffers within the input/output controller via a direct memory access.
    Type: Grant
    Filed: December 14, 1987
    Date of Patent: September 19, 1989
    Assignee: Unisys Corp.
    Inventors: Thomas E. Idleman, Jesse I. Stamness
  • Patent number: 4864532
    Abstract: A peripheral controller executes data transfer operations between a host computer and a multiple number of separate peripheral terminal units. A specialized buffer memory control system provides dedicated page-segments for each one of the peripheral terminal units to enable the peripheral controller to concurrently manage a multiple number of data transfer cycles in an optimum fashion in order to increase the through-put of the data transfer operations.
    Type: Grant
    Filed: September 21, 1987
    Date of Patent: September 5, 1989
    Assignee: Unisys Corporation
    Inventors: Jeffrey T. Reeve, Rangaswamy P. Giridhar
  • Patent number: 4858147
    Abstract: A network of N parallel processors are each one cross-connected to each other. Each cross connection includes a nodal weight delay circuit which carries status information as to whether a processor is "on" (=1) or "off" (=0) and whether its weighted influence (w.sub.ij) is excitatory or inhibitory as between the two processors i and j on that cross connection. Additionally, the cross connection influence between a processor i and a processor j is time delayed with a selectively fixed set of machine cycles between any two processor i and j. A monitoring processor-controller senses when the majority of processors have achieved a stable non-changing state which will represent an optimum solution for a combinatorial problem.
    Type: Grant
    Filed: June 15, 1987
    Date of Patent: August 15, 1989
    Assignee: Unisys Corporation
    Inventor: Peter R. Conwell
  • Patent number: 4851965
    Abstract: An enclosed mini-plenum is inserted between printed circuit boards to direct cooling air of various amounts into selected areas of the printed circuit board. The mini-plenum provides orifices of varying sizes to direct amounts of cooling airflow to aligned heat sinks on the printed circuit board. Certain orifices may have raised foils or leaves which can further direct selected amounts of airflow through the orifices. This system provides specifically controlled amounts of cooling facilities to printed circuit board areas having different heat dissipation requirements.
    Type: Grant
    Filed: May 23, 1988
    Date of Patent: July 25, 1989
    Assignee: Unisys Corporation
    Inventors: Paul G. Gabuzda, Sanford V. Terrell
  • Patent number: 4844565
    Abstract: A quick-set engaging and release spacer-connector assembly permits two cabinet modules to be fixedly connected side-by-side by manual operation of upper and lower internal lever handles which sit inside the assembly. A lateral drawing force operates to seal the cabinet modules with RFI/EMI gaskets on the periphery of each side of the spacer connector assembly.
    Type: Grant
    Filed: January 11, 1988
    Date of Patent: July 4, 1989
    Assignee: Unisys Corporation
    Inventors: James M. Brafford, Ralph H. Maeda
  • Patent number: 4833397
    Abstract: A tester-verifier apparatus operates to select a single one of a plurality of system clocks to verify that the clock width falls between accepted parameters. Secondarily, the apparatus selects representative clock signals for comparison with a reference clock to verify that the skew falls within accepted parameters. Additionally the apparatus can measure the exact time value of any pulse width or skew relationship to within 500 picoseconds (10.sup.-12). Any selected system clock signal is split into two channels, one of which has a controlled delay time programmed by a microprocessor to develop minimum and maximum pulse parameters against which the selected clock signal is logically compared to see if the parameters are satisfied.
    Type: Grant
    Filed: April 6, 1987
    Date of Patent: May 23, 1989
    Assignee: Unisys Corporation
    Inventor: Frank McMurray, Jr.
  • Patent number: 4815016
    Abstract: An apparatus and method are provided for automatically converting a bottom-up software representation of a logical circuit design, such as created by a computer aided design (CAD) system, into a behavioral software representation which can be simulated at relatively high speed.
    Type: Grant
    Filed: July 24, 1986
    Date of Patent: March 21, 1989
    Assignee: Unisys Corp.
    Inventor: Pamela J. Young
  • Patent number: 4808900
    Abstract: Disclosed is a servo control system for a disk drive actuator using a bi-directional (Up/Down) Difference Counter along with a control circuit therefor which signals the counter each time a "rest position" is passed, indicating whether this passage is toward, or away-from, the destination track.
    Type: Grant
    Filed: March 2, 1987
    Date of Patent: February 28, 1989
    Assignee: Unisys Corp.
    Inventors: Wilhelm Ohlinger, Nicholas M. Warner
  • Patent number: 4809279
    Abstract: A wide ROM-PROM memory is structured of multiple memory chips in parallel plus an auxiliary parity memory chip to hold parity bits for each corresponding addressable location in each memory chip. Sensing means is provided to check parity of data bits read from each memory location to verify integrity of the read-out.
    Type: Grant
    Filed: September 8, 1986
    Date of Patent: February 28, 1989
    Assignee: Unisys Corporation
    Inventors: Dongsung R. Kim, Reinhard K. Kronies
  • Patent number: 4809278
    Abstract: A parity detection scheme for a wide memory structure of RAM memory chips provides an auxiliary RAM parity memory chip to store parity data for each corresponding input line of each memory chip corresponding for each address of each memory chip. This parity data is compared to comparable parity data which is read-out of any corresponding address of each of said memory chips.
    Type: Grant
    Filed: April 21, 1986
    Date of Patent: February 28, 1989
    Assignee: Unisys Corporation
    Inventors: Dongsung R. Kim, Reinhard K. Kronies
  • Patent number: 4805090
    Abstract: A storage module device-data link processor provides for management of data transfer operations between a main host computer system and up to eight separate disk drive units. The data link processor provides a peripheral interface circuit unit (for selection of a given disk drive unit) and which is connected to a formatter circuit unit and a host adapter access circuit unit. The formatter unit establishes the required protocol format for addressing and accessing a particular cylinder, a particular head track and a particular sector within the selected disk drive unit. The host access unit connects the data link processor to the main host computer while also managing execution of the data transfer operations, including error correction and integrity checking.
    Type: Grant
    Filed: September 27, 1985
    Date of Patent: February 14, 1989
    Assignee: UNISYS Corporation
    Inventor: Ronald S. Coogan
  • Patent number: 4803655
    Abstract: An execute module in a data processing system is provided with a randomly accessible scratchpad memory which is logically divided into two switchable pages. During operation one page can be written with new instruction data from a fetch module while a previously written page is concurrently being read by the execute module for execution of a designated data processing operation. When the execute module completes execution and requires a new block of data, the two pages are logically switched by toggling an address bit.
    Type: Grant
    Filed: December 28, 1987
    Date of Patent: February 7, 1989
    Assignee: Unisys Corp.
    Inventor: Laurence P. Flora
  • Patent number: 4796109
    Abstract: A method for measuring bit shift and other characteristics indicative of the performance of a magnetic storage system, particularly for a system employing a thin-film magnetic head. In a preferred embodiment, complementary patterns are written many times around a circular track of a magnetic disk, each pattern including relatively closely spaced magnetic transitions as well as relatively widely spaced magnetic transitions. The relatively widely spaced transitions are chosen so as to be substantially unaffected by any other transitions. Measurements are made with reference to these widely spaced transitions and averaged for the many patterns recorded in the track so as to rapidly provide highly reliable measurements indicative of system performance.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: January 3, 1989
    Assignee: Unisys Corp.
    Inventors: Frank J. Sordello, Andrew M. Rose
  • Patent number: 4780570
    Abstract: Improved EMI/RFI shielding is provided for situations which require heavy duty wiping insertions, such as occurring when a relatively heavy electronic assembly is to be removably inserted in a cabinet. In accordance with the invention, inexpensive integral EMI/RFI strips of conductive spring material are riveted to opposite cabinet walls so as to be adjacent the wiping sides of the inserted electronic assembly. Each EMI/RFI strip contains integral longitudinally spaced projecting fingers formed to provide durable and highly reliable EMI/RFI shielding capable of withstanding many insertions and removals.
    Type: Grant
    Filed: March 30, 1987
    Date of Patent: October 25, 1988
    Assignee: Unisys Corporation
    Inventor: Ted Chuck
  • Patent number: 4755704
    Abstract: Apparatus for providing automatic clock de-skewing for a plurality of circuit boards of a data processing system. In a preferred embodiment, each circuit board is of multi-layer construction and contains a clock distribution chip which includes on-chip automatic clock de-skewing circuitry for providing de-skewed clocks to other chips on the circuit board. In a preferred implementation of the clock de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate reference delay are employed in conjunction with a phase comparator for automatically providing de-skewed clocks at the clock outputs of the clock distribution chip. The accurate reference delay is advantageously provided by a strip transmission line formed in a conductive layer of the multi-layer board containing the chips.
    Type: Grant
    Filed: June 30, 1987
    Date of Patent: July 5, 1988
    Assignee: Unisys Corporation
    Inventors: Laurence P. Flora, Michael A. McCullough
  • Patent number: 4754164
    Abstract: A method of providing automatic clock de-skewing for integrated circuit chips carried by a multi-layer circuit board. In a preferred implementation of the method, a clock distribution chip includes on-chip automatic clock de-skewing circuitry requiring an accurate reference delay which is advantageously provided by a strip transmission line formed on one of the conductive planes of the multi-layer circuit board containing the chips.
    Type: Grant
    Filed: June 30, 1984
    Date of Patent: June 28, 1988
    Assignee: Unisys Corp.
    Inventors: Laurence P. Flora, Michael A. McCullough