Abstract: A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address.

Abstract: An interactive terminal computer system is disclosed having a system bus for communicating between elements of the computer system which has apparatus for permitting the execution of a maximum number of concurrent bus cycles without interference with each other.

Abstract: An apparatus for encoding data for serial transmission wherein only logic ZEROs are transmitted as electronic pulses, each pulse alternating in opposite direction and wherein logic ONEs require no pulse.

Abstract: A method and apparatus for addressing a peripheral interface by mapping into the memory address space of a processor contained in a peripheral controller. The processor in the peripheral controller initializes interface logic within the peripheral controller and in the host system peripheral interface logic to which the peripheral controller is attached to either transmit or receive a block of data. Once initialized, units of data are transmitted across the interface between the peripheral controller and host system using a strobe and acknowledge signal to indicate when data can be taken or placed on data lines. The processor is placed in a wait state as each unit of data is transferred and a watch dog timer is provided to detect any transfer that is not completed within the normal response time of the interface.

Abstract: An interactive computer terminal system having a bus for communication between elements of the system is disclosed having apparatus for assigning control of the computer bus on a predetermined order of priority. The CPU receives requests from computer system elements and assigns time slots for use of the system bus by arbitrating among various resources competing for access to the bus.

Abstract: A diskette read data recovery system generates a clock which is locked to an incoming data stream. In a phase locked loop, a signal generated by an oscillator and frequency dividers is compared in phase to the incoming data stream to provide first or second signals depending on whether the incoming data signal leads or lags the clock signal. In order that the system may handle different types of incoming signals, different frequency divider circuits in the phase locked loop are selected for different incoming signals.

Abstract: A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of bit wide chips containing a predefined small number of row or column faults randomly distributed. System columns of chips are organized into a plurality of groups or slices, each of which provide a different predetermined portion of the locations within the partially good bulk memory. A defective-free memory having substantially less capacity is similarly organized. Both memories couple to a static memory which is remapped under the control of the microprocessing section. Prior to remapping, the microprocessing section generates a "slice bit map" indicating the results of testing successive bit groups/slices within the bulk memory locations.

Abstract: In a data processing system, a stack mechanism creates a stack of operands in a series of memory locations. The memory locations are grouped into stack frames corresponding to the operands included within individual procedures executed by a processing unit of the data processing system. The stack has a maximum number of allocatable storage locations with the actual physical size of the stack being equal to the total number of operands stored therein. The size of the stack is dynamically alterable to conserve usable storage locations in the memory and accessing of operands within a stack frame can be relative to the top or bottom of the stack frame.

Abstract: A memory controller includes a partial defective bulk random access memory having a number of word locations constructed from a plurality of bit wide chips containing a predefined small number of random row or column faults. System columns of chips are organized into a plurality of groups, each group providing a different predetermined portion of the number of word locations. A defect-free memory system having substantially less capacity is similarly organized. Both memories couple to a static memory which stores column addresses associated with good memory locations and slice bit codes specifying the operational status of corresponding bit groups of word locations within both memories. During operation, read/write control circuits read and write valid words from group of bit locations from locations of both memories specified by slice bit codes.

Abstract: An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a common information path to plural data processing units including memory units, peripheral control units, central processing units and ISL units, and wherein each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs. The error detection system requires no special supporting software or firmware on the part of any data processing unit on any of the communication busses.

Abstract: A hardware monitoring interface unit (HMIU) is coupled to a data processing unit and receives all information transferred between subsystems of the data processing unit. Programmable hit matrices (PHM's) include input latches for receiving the information, memory circuits for storing binary ONE's in locations addressed by predetermined portions of the information and output latches for storing the binary ONE's or "hit" signals read from the memory circuits. The "hit" signals are plug-wired into logic circuits and counters in a monitor to collect statistical data.

Abstract: A video generation logic for a display controller includes a precoded PROM which combines visual attributes associated with the characters of information to be displayed on the display screen to produce multiple video control signals for modifying the dot pattern generation signal which is generated in response to character information stored in a refresh memory of the display controller. Visual attribute signals are used as an address to a video attribute generation PROM to retrieve a precoded data word associated with a particular combination of video attributes and the information contained in the retrieved data word is used to provide video control signals. Some of the video control signals are combined with the dot pattern generation signal to provide a video signal which is transmitted to the display monitor which displays the character information.

Abstract: A high speed link controller (HSLC) and a number of work stations are coupled in common to a single conductor coaxial cable. Apparatus generates data signals at high speed for transfer of information between the link controller and the work stations with reduced reflections.

Abstract: An interactive terminal system includes a high speed link controller (HSLC) and a number of work stations, all coupled in common to a single conductor coaxial bus. The HSLC includes apparatus controlled by a microprocessor to put the HSLC in a wraparound test mode. The microprocessor transfers test bytes which pass through the HSLC logic and are checked by the microprocessor.

Abstract: A method and apparatus for generating a repetitive serial pattern using a recirculating shift register. Use of a recirculating shift register during a disk formatting operation permits a reduction in the amount of memory contained in a peripheral controller that would otherwise be required to format the disk prior to its being available for normal write and read operations.

Abstract: An auto address development logic that, when provided a starting address, is used to develop consecutive addresses as multiple words of information are presented, one word at a time, during multiple consecutive information transfer cycles. The logic retains for use a current address while simultaneously developing the next address so that the next address will be immediately available as the current address at the beginning of the next information transfer cycle. The auto address development logic is used in a system analyzer connected to a data processing system having a common bus over which the CPU, during a first bus cycle, provides a starting address and requests that the memory fetch multiple words of information which are transferred to the CPU, during multiple subsequent responding bus cycles.

Abstract: A method and apparatus for defining magnetic disk track field lengths using a programmable counter. Use of a programmable counter in a disk controller permits a reduction in the amount of combinational logic that would otherwise be required to be able to perform the various formatting, reading and writing operations involved in use of just one type of disk and makes it possible to perform these operations on a wide variety of disks having different track and sector formats.

Abstract: A data processing system includes a high speed link controller coupled to a number of work stations by a single coaxial conductor. Apparatus including a counter, a comparator and an adder in the high speed controller synchronizes the data bits received from the work stations to the high speed controller clocking system.