Patents Represented by Attorney, Agent or Law Firm Norman R. Klivans
  • Patent number: 6492797
    Abstract: A method and apparatus for calibrating tester timing accuracy during testing of integrated circuits. An ATE tester measures itself through reference blocks that have the same relevant dimensions as the integrated circuits to be tested. The number of reference blocks required is equal to the number of signal terminals on an integrated circuit to be tested being subject to timing calibration. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block. Each signal trace used should be closely matched both physically and electrically to the other signal traces used in the set of reference blocks, so that the electrical path length associated with each trace is nearly identical. To perform the timing calibration, the reference blocks may be mounted on a single fixture one at a time, or using multi-site fixtures, multiple reference blocks may be used in parallel.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: December 10, 2002
    Assignee: Schlumberger Technologies, Inc.
    Inventors: Howard M. Maassen, William A. Fritzsche, Thomas P. Ho, Joseph C. Helland
  • Patent number: 6493840
    Abstract: A testability architecture and method for loosely integrated (modularized) integrated circuits uses stand alone module testing. For an integrated circuit chip which has a number of independent modules, where one module design is used in a number of different chips, each module is connected to the chip's input/output pins and to a configuration module. To make testing of the modules more efficient and less expensive, during testing of the chip a particular module design is confronted with the same testing environment regardless of the actual chip in which it is present. Advantageously, chip area is only slightly enlarged by the test circuitry. A test architecture of the configuration module includes test registers and carries out a standard protocol for all read and write transactions during testing. This approach provides better test coverage and economizes in test generation.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: December 10, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Alon Shacham, Peleg Lior, Rami Saban, Yomtov Sidl
  • Patent number: 6489636
    Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: December 3, 2002
    Assignee: LumiLeds Lighting U.S., LLC
    Inventors: Werner K. Goetz, Michael D. Camras, Nathan F. Gardner, R. Scott Kern, Andrew Y. Kim, Stephen A. Stockman
  • Patent number: 6490727
    Abstract: In hybrid fiber coaxial cable networks such as used in cable television where two-way digital communications are desired, a distributed termination system is provided. In such a system the home terminals are digital terminals, such as digital set-top boxes or cable modems using bi-directional transmission standards. The functionality of the head end controller in a conventional system is in this system distributed between the head end and the fiber nodes which link the coaxial cable and optical fiber portions of the system. Thereby the upstream detection takes place in the fiber nodes rather than in the head end by placing upstream burst receivers in the fiber nodes. Further there is a distributed method to enable this by providing synchronization and calibration control between the head end and the fiber nodes. Also, the return path is a digital return path supported by having the burst receivers located in the fiber nodes.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: December 3, 2002
    Assignee: Harmonic, Inc.
    Inventors: Moshe Nazarathy, Adi Bonen, Ilan Kepten, David Piehler
  • Patent number: 6486499
    Abstract: The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: November 26, 2002
    Assignee: LumiLeds Lighting U.S., LLC
    Inventors: Michael R Krames, Daniel A. Steigerwald, Fred A. Kish, Jr., Pradeep Rajkomar, Jonathan J. Wierer, Jr., Tun S Tan
  • Patent number: 6479323
    Abstract: A method and structure for attaching a lead frame to a heat sink are provided. In one embodiment, a layer of thermally conductive, electrically insulating epoxy is formed on a heat sink and the epoxy layer is fully cured. A thermoplastic adhesive layer is formed on the epoxy layer, and the heat sink is clamped to the lead frame such that the thermoplastic layer contacts the lead frame. The thermoplastic layer is heated to its melting point and then cooled, thereby joining the heat sink and the lead frame. In a variation, a partially cured B-stage epoxy layer is used to replace the thermoplastic layer. The B-stage epoxy layer is fully cured to connect the lead frame to the heat sink.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: November 12, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Randy H. Y. Lo, Boonmi Mekdhanasarn, Daniel P. Tracy
  • Patent number: 6476830
    Abstract: A virtual world computer process includes portable virtual token objects that can be used by on-line users of the virtual world to facilitate exchange of goods and services within the virtual world. In particular, client-server computer processes are provided for the virtual world that allow on-line users to conduct activities within the virtual world including getting, putting, giving, and receiving portable virtual token objects as well as other portable virtual objects. Each on-line user is represented in the graphic user interface by a virtual avatar object. Token objects are put into circulation by virtual ATM objects. A virtual ATM object allows a user to obtain a balance, deposit tokens, and withdraw tokens. A vendroid object is an object that sells portable virtual items in exchange for tokens deposited by avatars. Different virtual items have different values, and vendroids do not all have the same virtual items for sale. In the virtual world, a lurker is represented in a locale by a ghost object.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: November 5, 2002
    Assignee: Fujitsu Software Corporation
    Inventors: Randy Farmer, Chris Morningstar, John E. Onusko, Norman Morse
  • Patent number: 6475369
    Abstract: An electroplating method includes forming a layer, the forming of the layer includes: a) contacting a substrate with a first article, the first article includes a support and a conformable mask disposed in a pattern on the support; b) electroplating a first metal from a source of metal ions onto the substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the substrate. The method may further involve one or more of (1) selectively depositing or non-selectively depositing one or more additional materials to complete formation of the layer, (2) planarizing deposited material after each deposition or after all depositions for a layer, and/or (3) forming layers adjacent previously formed layers to build up a structure from a plurality of adhered layers. Electroplating articles and electroplating apparatus are also disclosed.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: November 5, 2002
    Assignee: University of Southern California
    Inventor: Adam L. Cohen
  • Patent number: 6473598
    Abstract: A radio frequency signal processing system such as an LMDS transceiver includes a receive switch, a first signal reception processing block, a second signal reception processing block, a transmit switch, a first signal transmission processing block, a second signal transmission processing block, and a controller to transmit the incoming radio frequency signal to a selected one of the first and second signal reception processing blocks, and causes the transmit switch to receive the outgoing radio frequency signal from a selected one of the first and second signal transmission processing blocks. Multiple frequency ranges may therefore be handled by a single LMDS transceiver, enabling low-cost mass production of the transceiver.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: October 29, 2002
    Inventor: Fareed Sepehry-Fard
  • Patent number: 6472777
    Abstract: In a stage assembly, for instance a fine stage using a pair of push-pull electro-magnetic actuators to move the stage back and forth along an axis, there is typically a sensor to determine the actual stage location. This sensor's home position must correspond to the actual stage position where the two opposed actuators are observed to exert forces of the same magnitude but opposing directions on this stage. Since the actuators depend on the sensor reading to exert their forces correctly, misalignment of the home position will decrease system performance. The calibration of this sensor is accomplished using actual system feedback signals, which are the currents drawn by the two opposed actuators, during run time conditions. The sensor is considered calibrated (meaning a virtual “null” position) when each of the two opposed actuators draws the same amount of current. If this is not the case a feedback process calibrates the sensor.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: October 29, 2002
    Assignee: Nikon Corporation
    Inventors: Ting-Chien Teng, Bausan Yuan
  • Patent number: 6469314
    Abstract: An LED and a method of fabricating the LED which utilize controlled oxygen (O) doping to form at least one layer of the LED having an O dopant concentration which is correlated to the dominant emission wavelength of the LED. The O dopant concentration is regulated to be higher when the LED has been configured to have a longer dominant emission wavelength. Since the dominant emission wavelength is dependent on the composition of the active layer(s) of the LED, the O dopant concentration in the layer is related to the composition of the active layer(s). The controlled O doping improves the reliability while minimizing any light output penalty due to the introduction of O dopants. In an exemplary embodiment, the LED is an AlGaInP LED that includes a substrate, an optional distributed Bragg reflector layer, an n-type confining layer, an optional n-type set-back layer, an active region, an optional p-type set-back layer, a p-type confining layer and an optional window layer.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: October 22, 2002
    Assignee: LumiLeds Lighting U.S., LLC
    Inventors: Patrick N. Grillot, Eugene I. Chen, Jen-Wu Huang, Stephen A. Stockman
  • Patent number: 6459097
    Abstract: A solid-state quantum computing structure includes a set of islands that Josephson junctions separate from a first superconducting bank. A d-wave superconductor is on one side of the Josephson junctions (either the islands' side or the bank's side), and an s-wave superconductor forms the other side of the Josephson junctions. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: October 1, 2002
    Assignee: D-Wave Systems Inc.
    Inventor: Alexandre M. Zagoskin
  • Patent number: 6449031
    Abstract: A method for forming a critical dimension test mark, and the use of the mark to characterize and monitor imaging performance is provided. Methods in accordance with the present invention encompass an exposure of an essentially standard critical dimension bar at each of two overlapping orientations that are rotated about an axis with respect to each other. The overlapped portion forming a critical dimension test mark that is useful for enabling low cost, rapid determination of sub-micron critical dimensions for characterizing exposure tool imaging performance and in-process performance monitoring using optical measurement systems.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: September 10, 2002
    Assignees: Nikon Corporation, Nikon Precision, Inc.
    Inventors: Ilya Grodnensky, Kyoichi Suwa, Kazuo Ushida, Eric R. Johnson
  • Patent number: 6441393
    Abstract: A semiconductor device is provided having n-type device layers of III-V nitride having donor dopants such as germanium (Ge), silicon (Si), tin (Sn), and/or oxygen (O) and/or p-type device layers of III-V nitride having acceptor dopants such as magnesium (Mg), beryllium (Be), zinc (Zn), and/or cadmium (Cd), either simultaneously or in a doping superlattice, to engineer strain, improve conductivity, and provide longer wavelength light emission.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: August 27, 2002
    Assignee: LumiLeds Lighting U.S., LLC
    Inventors: Werner Goetz, R. Scott Kern
  • Patent number: 6429904
    Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: August 6, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
  • Patent number: 6425046
    Abstract: A fault-tolerant, high-speed wafer scale system includes a plurality of functional memory modules, each having associated sense amplifiers which act as high-speed cache memory, a parallel hierarchical bus which is fault-tolerant to defects and a interconnect network, and one or more bus masters. By grouping the DRAM arrays into logically independent modules of relatively small memory capacity (588 Kbit), a large number of cache lines (128) is obtained at small main memory capacity (4 Megabytes). The large number of cache lines allows maintaining a high cache hit rate (greater than 90%).
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: July 23, 2002
    Assignee: Monolithic System Technology, Inc.
    Inventors: Wing Yu Leung, Fu-Chieh Hsu
  • Patent number: 6423612
    Abstract: A shallow trench isolation (STI) region is covered with a nitride layer. The nitride layer, advantageously, fills in gaps in the underlying dielectric layer, such as seams, thereby reducing leakage. The nitride layer may be patterned to form a spacer above the STI region which is used to define an opening in the polysilicon layer that is subsequently deposited. The polysilicon layer is etched back to expose the nitride spacer, which is then etched away in a controlled fashion. Thus, a small opening may be formed in the polysilicon layer. Further, because the polysilicon layer is etched back to the top of the nitride spacer, the polysilicon layer is planarized thereby reducing stringers in subsequent processing.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: July 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wenge Yang, John Jianshi Wang, Fei Wang
  • Patent number: 6415429
    Abstract: A programmable analogue device including an array of cells. Each cell is controllable for performing a predetermined set of analogue functions. The cells are selectively interconnected for programming selected analogue circuits. Each cell includes an array of subcells, an output circuit coupled to each of the subcells for delivering an analogue output as determined by the analogue function of an activated subcell, and a function control circuit for activating a particular subcell in dependence upon a function select input. Each subcell performs one of the analogue functions among the predetermined set, and includes a differential pair of transistors defining an operational amplifier with the input bias circuit. Each subcell is activated using a series switch in the subcell which couples the subcell to an input bias circuit; the series switch in each subcell is in turn coupled to and controllable by the function control circuit.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: July 2, 2002
    Inventor: David Latham Grundy
  • Patent number: 6406636
    Abstract: Wafer-to-wafer bonding using, e.g., solder metal bonding, glass bonding or polymer (adhesive) bonding is improved by profiling one or both of the wafer surfaces being bonded to define microstructures therein. Profiling means providing other than the conventional planar bonding surface to define cavities therein. The bonding material fills the cavities in the microstructures. For instance, a system of ridges and trenches (e.g. in cross-section vertical, slanted, key-holed shaped, or diamond-shaped) are microstructures that increase the surface area of the wafers to which the bonding material can adhere. Use of the key-hole shaped or diamond-shaped profile having a negative slope at the trench interior substantially increases the bonding force.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: June 18, 2002
    Assignee: MegaSense, Inc.
    Inventor: Vladimir I. Vaganov
  • Patent number: 6404889
    Abstract: A VGA (or other component video signal) output, e.g. from a computer or DVD player, is protected so it is viewable on a VGA monitor. However, if the component video signal is converted to composite video (e.g. television) the resulting television picture is of substantially degraded quality, thereby inhibiting viewing and/or copying. This protects for instance copyrighted material in the VGA format from unauthorized use. The protection involves modifying the horizontal or vertical synchronization signals in the VGA video in such a way that there is no adverse affect on a typical VGA monitor. However, most or all VGA to television converters and/or television sets and VCR's suffer from loss of synchronization, resulting in an unviewable picture. Also, methods and circuits for defeating the copy protection are provided.
    Type: Grant
    Filed: October 13, 1997
    Date of Patent: June 11, 2002
    Assignee: Macrovision Corporation
    Inventors: John O. Ryan, Kordian J. Kurowski, Ronald Quan