Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
Type:
Grant
Filed:
October 31, 2007
Date of Patent:
June 30, 2009
Assignee:
Ziptronix, Inc.
Inventors:
Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
Abstract: A semiconductor integrated circuit device includes even-numbered bit lines, odd-numbered bit lines, cell source lines, first memory elements electrically connected between the even-numbered bit lines and the cell source lines, and second memory elements electrically connected between the odd-numbered bit lines and the cell source lines and belonging to the same rows as the first memory elements. A potential corresponding to data to be programmed is applied to the first memory element via the even-numbered bit line and a potential which suppresses programming is applied to the second memory element via the cell source line while the odd-numbered bit lines are kept in an electrically floating state when data is programmed into the first memory element.
Abstract: A sialon type phosphor in the form of a powder comprising at least 40 wt % of &agr;-sialon represented by the formula (Cax,My)(Si,Al)12(O,N)16 (where M is at least one metal selected from the group consisting of Eu, Tb, Yb and Er, 0.05<(x+y)<0.3, 0.02<x<0.27 and 0.03<y<0.3) and having a structure such that Ca sites of Ca-&agr;-sialon are partially substituted by other metal M, at most 40 wt % of &bgr;-sialon, and at most 30 wt % of unreacted silicon nitride.
Type:
Grant
Filed:
June 6, 2002
Date of Patent:
October 14, 2003
Assignee:
National Institute for Materials Science