Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

Abstract: The disclosed embodiments provide a system that filters duplicate requests from an L1 cache for a cache line. During operation, the system receives at an L2 cache a first request and a second request for the same cache line, and stores identifying information for these requests. The system then performs a cache array look-up for the first request that, in the process of creating a load fill packet for the first request, loads the cache line into a fill buffer. After sending the load fill packet for the first request to the L1 cache, the system uses the cache line data still stored in the fill buffer and stored identifying information for the second fill request to send a subsequent load fill packet for the second request to the L1 cache without performing an additional cache array look-up.

Abstract: One embodiment of the present invention provides a solar cell. The solar cell includes a metallurgical-grade Si (MG-Si) substrate, a first layer of heavily doped crystalline-Si situated above the MG-Si substrate, a layer of lightly doped crystalline-Si situated above the first heavily doped crystalline-Si layer, a backside ohmic-contact layer situated on the backside of the MG-Si substrate, a second layer of heavily doped crystalline-Si situated above the lightly doped crystalline-Si layer, a first layer of dielectric situated above the second heavily doped crystalline-Si layer, a second layer of dielectric situated above the first dielectric layer, and front electrodes situated above the second dielectric layer.

Abstract: A system and method are provided for inlining a program call between processes executing under separate ISAs (Instruction Set Architectures) within a system virtual machine. The system virtual machine hosts any number of virtual operating system instances, each of which may execute any number of applications. The system virtual machine interprets or dynamically compiles not only application code executing under virtual operating systems, but also the virtual operating systems. For a program call that crosses ISA boundaries, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the virtual ISA of the code. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions are configured and executed (or emulated) to perform as they would within the virtual ISA.

Abstract: A system that determines if a DNS server suffers from a particular known functional limitation. During operation, the system sends an exploratory query to the DNS server, wherein the exploratory query is specially constructed so as to detect the existence of a functional limitation in the DNS server without causing the DNS server to fail. Next, the system receives an answer to the exploratory query from the DNS server. If the DNS server gives an incorrect response, the system can take actions as may be desired for the implementation. For example, the system may display a message identifying the functional limitation, or the system may establish a mode of operation where it avoids performing those types of DNS queries known to present a risk of crashing the particular Internet gateway.

Abstract: A comparison technique for efficiently comparing an input string to a set of strings is described. This set of strings may be represented in a tree structure as paths from a root of the tree structure to leaves of the tree structure, and strings in the set of strings that share common substrings share nodes in the tree structure. During the comparison technique, labels may be assigned to a given node in the tree structure based at least in part on comparisons between a given character in the input string and a character associated with the given node. These labels may include a position of the given character in the input string, and a cumulative error between the characters in a string that are associated with a branch in the tree structure and the characters in the input string that have been processed. Based at least in part on these labels, an actual string, which corresponds to the input string, may be identified.

Abstract: A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There can be a random choice of available scrambler seeds for any particular chunk to avoid malicious forcing of zero and one patterns or run lengths of bit zeroes and ones. There are a chunk cyclical redundancy check (CRC) as well as forward error correction (FEC) bytes to detect and/or correct any errors and also to insure a high degree of data and control integrity.

Abstract: One embodiment of the present invention provides a system for facilitating a game that operates within a social-networking application. During operation, the system receives a request from a user to participate in a game that is running within the social-networking application, wherein the request is received at the game. Next, in response to the request, the system adds the user to the game. The system then receives a notification at the game that the user has performed an action within the social network. Next, in response to the notification, the system determines a point value assigned to the action. Finally, the system increments a score associated with the user by the point value.

Abstract: One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a failure state of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides an advice state associated with the recorded failure state to the program to facilitate a response to the transaction failure by the program.

Abstract: One embodiment provides a technique for analyzing a target electromagnetic signal radiating from a monitored system. During the technique, the monitored system is positioned at a first locus of an ellipsoidal surface to amplify the target electromagnetic signal received at a second locus of the ellipsoidal surface. Next, the amplified target electromagnetic signal is monitored using an antenna positioned at the second locus of the ellipsoidal surface. Finally, the integrity of the monitored system is assessed by analyzing the amplified target electromagnetic signal monitored by the antenna.

Abstract: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation.

Abstract: One embodiment of the present invention provides a system that detects sensitive content in a document. In doing so, the system receives a document, identifies a set of terms in the document that are candidate sensitive terms, and generates a combination of terms based on the identified terms that is associated with a semantic meaning. Next, the system performs searches through a corpus based on the combination of terms and determines hit counts returned for each term in the combination and for the combination. The system then determines whether the combination of terms is sensitive based on the hit count for the combination and the hit counts for the individual terms in the combination, and generates a result that indicates portions of the document which contain sensitive combinations.

Abstract: Some embodiments of the present invention provide a system that processes a phone call. During operation, the system connects the phone call from a mobile phone and determines whether the phone call is an emergency call. If the phone call is an emergency call, the system activates an emergency mode of the mobile phone to handle the phone call, which prolongs the length of the phone call.

Abstract: A new “held” (“H”) cache-coherency state is introduced for directory-based multiprocessor systems. Using the held state enables embodiments of the present invention to track sharers that have a shared copy of a cache line after a directory runs out of space for holding information that identifies processors that have received shared copies of the cache line (e.g., pointers to sharers of the cache line). In these embodiments, when a directory entry is full, the system provides subsequent shared copies of the cache line to sharers in the held state and tracks the identity of the held-copy owners in a data field in the entry for the cache line in a home node.

Abstract: The described embodiments include a processor that handles faults during execution of a vector instruction. The processor starts by receiving a vector instruction that uses at least one vector of values that includes N elements as an input. In addition, the processor optionally receives a predicate vector that includes N elements. The processor then executes the vector instruction. In the described embodiments, when executing the vector instruction, if the predicate vector is received, for each element in the vector of values for which a corresponding element in the predicate vector is active, otherwise, for each element in the vector of values, the processor performs an operation for the vector instruction for the element in the vector of values. While performing the operation, the processor conditionally masks faults encountered (i.e., faults caused by an illegal operation).

Abstract: Some embodiments of the present invention provide a system that facilitates interaction with a user of a computing device. During operation, the system obtains user input from the user through a user interface of the computing device. Next, the system updates, based on the user input, a dynamic cursor area proximate to a cursor in the user interface to provide functionality-based feedback to the user at a location where the user is likely to be looking.

Abstract: Some embodiments of the present invention provide a system that measures the quality of a software system. During operation, the system performs a series of stress tests on the software system and determines a set of failure rates for the software system from the stress tests. Next, the system obtains a failure distribution from the failure rates. Finally, the system assesses the quality of the software system based on characteristics of the failure distribution.

Abstract: An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic.

Abstract: Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is distributed to buffer ingress managers. Within a set of ingress managers serving one buffer, each manager corresponds to one function of the buffer's corresponding host, and is programmed with criteria for identifying packets desired by that function. One copy of the packet is stored in a buffer if at least one of the buffer's ingress managers accepts it, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions.

Abstract: A multi-chip module (MCM), which includes a three-dimensional (3D) stack of chips that are coupled using optical interconnects, is described. In this MCM, disposed on a first surface of a middle chip in the 3D stack, there are: a first optical coupler, an optical waveguide, which is coupled to the first optical coupler, and a second optical coupler, which is coupled to the optical waveguide. The first optical coupler redirects an optical signal from the optical waveguide to a first direction (which is not in the plane of the first surface), or from the first direction to the optical waveguide. Moreover, the second optical coupler redirects the optical signal from the optical waveguide to a second direction (which is not in the plane of the first surface), or from the second direction to the optical waveguide. Note that an optical path associated with the second direction passes through an opening in a substrate in the middle chip.